From: David Gibson <david@gibson.dropbear.id.au>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz <groug@kaod.org>
Subject: Re: [PATCH v4 03/25] ppc/pnv: Introduce a PNV_CHIP_CPU_FOREACH() helper
Date: Thu, 3 Oct 2019 11:50:17 +1000 [thread overview]
Message-ID: <20191003015017.GE11105@umbus.fritz.box> (raw)
In-Reply-To: <20190918160645.25126-4-clg@kaod.org>
[-- Attachment #1: Type: text/plain, Size: 2333 bytes --]
On Wed, Sep 18, 2019 at 06:06:23PM +0200, Cédric Le Goater wrote:
> As there is now easy way to loop on the CPUs belonging to a chip, add
> a helper to filter out external CPUs.
This seems a somewhat odd way to go about it, given that the chip does
have a cores array and the cores then have a threads array. What's
the difficulty with using that rather than looping through all vcpus
and filtering?
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/intc/pnv_xive.c | 23 ++++++++++++++++++++++-
> 1 file changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
> index ae449aa1119b..e1c15b6b5b71 100644
> --- a/hw/intc/pnv_xive.c
> +++ b/hw/intc/pnv_xive.c
> @@ -392,15 +392,36 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx,
> return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas);
> }
>
> +static int cpu_pir(PowerPCCPU *cpu)
> +{
> + CPUPPCState *env = &cpu->env;
> + return env->spr_cb[SPR_PIR].default_value;
> +}
> +
> +static int cpu_chip_id(PowerPCCPU *cpu)
> +{
> + int pir = cpu_pir(cpu);
> + return (pir >> 8) & 0x7f;
> +}
> +
> +#define PNV_CHIP_CPU_FOREACH(chip, cs) \
> + CPU_FOREACH(cs) \
> + if (chip->chip_id != cpu_chip_id(POWERPC_CPU(cs))) {} else
> +
> static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
> uint8_t nvt_blk, uint32_t nvt_idx,
> bool cam_ignore, uint8_t priority,
> uint32_t logic_serv, XiveTCTXMatch *match)
> {
> + PnvXive *xive = PNV_XIVE(xptr);
> CPUState *cs;
> int count = 0;
>
> - CPU_FOREACH(cs) {
> + /*
> + * Loop on all CPUs of the machine and filter out the CPUs
> + * belonging to another chip.
> + */
> + PNV_CHIP_CPU_FOREACH(xive->chip, cs) {
> PowerPCCPU *cpu = POWERPC_CPU(cs);
> XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
> int ring;
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
next prev parent reply other threads:[~2019-10-03 2:50 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-18 16:06 [Qemu-devel] [PATCH v4 00/25] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 01/25] ppc/xive: Introduce a XivePresenter interface Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 02/25] ppc/xive: Implement the " Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 03/25] ppc/pnv: Introduce a PNV_CHIP_CPU_FOREACH() helper Cédric Le Goater
2019-10-03 1:50 ` David Gibson [this message]
2019-10-03 9:42 ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 04/25] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper Cédric Le Goater
2019-10-03 1:51 ` David Gibson
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 05/25] ppc/xive: Introduce a XiveFabric interface Cédric Le Goater
2019-10-03 1:54 ` David Gibson
2019-10-03 9:46 ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 06/25] ppc/pnv: Implement the " Cédric Le Goater
2019-10-03 1:55 ` David Gibson
2019-10-03 9:47 ` Cédric Le Goater
2019-10-04 9:05 ` Greg Kurz
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 07/25] ppc/spapr: " Cédric Le Goater
2019-10-03 1:58 ` David Gibson
2019-10-03 9:50 ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 08/25] ppc/xive: Use the XiveFabric and XivePresenter interfaces Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 09/25] ppc/xive: Extend the TIMA operation with a XivePresenter parameter Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 10/25] ppc/pnv: Clarify how the TIMA is accessed on a multichip system Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 11/25] ppc/xive: Move the TIMA operations to the controller model Cédric Le Goater
2019-10-03 2:08 ` David Gibson
2019-10-03 10:57 ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 12/25] ppc/xive: Remove the get_tctx() XiveRouter handler Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 13/25] ppc/xive: Introduce a xive_tctx_ipb_update() helper Cédric Le Goater
2019-10-03 2:11 ` David Gibson
2019-10-03 9:30 ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 14/25] ppc/xive: Introduce helpers for the NVT id Cédric Le Goater
2019-10-03 2:12 ` David Gibson
2019-10-03 9:23 ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 15/25] ppc/xive: Synthesize interrupt from the saved IPB in the NVT Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 16/25] ppc/pnv: Remove pnv_xive_vst_size() routine Cédric Le Goater
2019-10-03 2:20 ` David Gibson
2019-10-03 9:12 ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 17/25] ppc/pnv: Dump the XIVE NVT table Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 18/25] ppc/pnv: Skip empty slots of " Cédric Le Goater
2019-10-03 2:22 ` David Gibson
2019-10-03 8:46 ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 19/25] ppc/pnv: Introduce a pnv_xive_block_id() helper Cédric Le Goater
2019-10-03 2:25 ` David Gibson
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 20/25] ppc/pnv: Extend XiveRouter with a get_block_id() handler Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 21/25] ppc/pnv: Quiesce some XIVE errors Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 22/25] ppc/xive: Introduce a xive_os_cam_decode() helper Cédric Le Goater
2019-10-03 2:34 ` David Gibson
2019-10-03 8:39 ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 23/25] ppc/xive: Check V bit in TM_PULL_POOL_CTX Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 24/25] ppc/pnv: Improve trigger data definition Cédric Le Goater
2019-10-03 2:41 ` David Gibson
2019-10-03 8:30 ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 25/25] ppc/pnv: Use the EAS trigger bit when triggering an interrupt from PSI Cédric Le Goater
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20191003015017.GE11105@umbus.fritz.box \
--to=david@gibson.dropbear.id.au \
--cc=clg@kaod.org \
--cc=groug@kaod.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).