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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id t17sm11962094wrp.72.2019.10.04.04.48.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Oct 2019 04:48:52 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [RFC 1/4] hw/timer/arm_timer: Add trace events Date: Fri, 4 Oct 2019 12:48:45 +0100 Message-Id: <20191004114848.16831-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191004114848.16831-1-peter.maydell@linaro.org> References: <20191004114848.16831-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add some basic trace events to the arm_timer device. Signed-off-by: Peter Maydell --- hw/timer/arm_timer.c | 27 +++++++++++++++++++++------ hw/timer/trace-events | 7 +++++++ 2 files changed, 28 insertions(+), 6 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index c2e6211188b..283ae1e74a9 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -17,6 +17,7 @@ #include "qemu/main-loop.h" #include "qemu/module.h" #include "qemu/log.h" +#include "trace.h" /* Common timer implementation. */ @@ -43,7 +44,10 @@ typedef struct { static void arm_timer_update(arm_timer_state *s) { /* Update interrupts. */ - if (s->int_level && (s->control & TIMER_CTRL_IE)) { + int level = s->int_level && (s->control & TIMER_CTRL_IE); + + trace_sp804_arm_timer_update(level); + if (level) { qemu_irq_raise(s->irq); } else { qemu_irq_lower(s->irq); @@ -216,17 +220,21 @@ static uint64_t sp804_read(void *opaque, hwaddr offset, unsigned size) { SP804State *s = (SP804State *)opaque; + uint64_t res; if (offset < 0x20) { - return arm_timer_read(s->timer[0], offset); + res = arm_timer_read(s->timer[0], offset); + goto out; } if (offset < 0x40) { - return arm_timer_read(s->timer[1], offset - 0x20); + res = arm_timer_read(s->timer[1], offset - 0x20); + goto out; } /* TimerPeriphID */ if (offset >= 0xfe0 && offset <= 0xffc) { - return sp804_ids[(offset - 0xfe0) >> 2]; + res = sp804_ids[(offset - 0xfe0) >> 2]; + goto out; } switch (offset) { @@ -236,12 +244,17 @@ static uint64_t sp804_read(void *opaque, hwaddr offset, qemu_log_mask(LOG_UNIMP, "%s: integration test registers unimplemented\n", __func__); - return 0; + res = 0; + goto out; } qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n", __func__, (int)offset); - return 0; + res = 0; + +out: + trace_sp804_read(offset, res); + return res; } static void sp804_write(void *opaque, hwaddr offset, @@ -249,6 +262,8 @@ static void sp804_write(void *opaque, hwaddr offset, { SP804State *s = (SP804State *)opaque; + trace_sp804_write(offset, value); + if (offset < 0x20) { arm_timer_write(s->timer[0], offset, value); return; diff --git a/hw/timer/trace-events b/hw/timer/trace-events index db02a9142cd..600b002c7bf 100644 --- a/hw/timer/trace-events +++ b/hw/timer/trace-events @@ -87,3 +87,10 @@ pl031_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" pl031_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" pl031_alarm_raised(void) "alarm raised" pl031_set_alarm(uint32_t ticks) "alarm set for %u ticks" + +# arm_timer.c +sp804_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" +sp804_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" +# Note that this trace event can't distinguish which of the two timers +# in the sp804 is being updated +sp804_arm_timer_update(int level) "level %d" -- 2.20.1