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From: "Cédric Le Goater" <clg@kaod.org>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: "Cédric Le Goater" <clg@kaod.org>,
	qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
	"Greg Kurz" <groug@kaod.org>
Subject: [PATCH 8/9] ppc/xive: Introduce OS CAM line helpers
Date: Mon,  7 Oct 2019 10:41:01 +0200	[thread overview]
Message-ID: <20191007084102.29776-9-clg@kaod.org> (raw)
In-Reply-To: <20191007084102.29776-1-clg@kaod.org>

The OS CAM line has a special encoding exploited by the HW. Provide
helper routines to hide the details to the TIMA command handlers. This
also clarifies the endianness of different variables : 'qw1w2' is
big-endian and 'cam' is native.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/intc/xive.c | 41 ++++++++++++++++++++++++++++++++++++++---
 1 file changed, 38 insertions(+), 3 deletions(-)

diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 2bf7b4ad7006..143418c232a2 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -337,14 +337,49 @@ static void xive_tm_set_os_pending(XiveTCTX *tctx, hwaddr offset,
     xive_tctx_notify(tctx, TM_QW1_OS);
 }
 
+static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk,
+                               uint32_t *nvt_idx, bool *vo)
+{
+    if (nvt_blk) {
+        *nvt_blk = xive_nvt_blk(cam);
+    }
+    if (nvt_idx) {
+        *nvt_idx = xive_nvt_idx(cam);
+    }
+    if (vo) {
+        *vo = !!(cam & TM_QW1W2_VO);
+    }
+}
+
+static uint32_t xive_tctx_get_os_cam(XiveTCTX *tctx, uint8_t *nvt_blk,
+                                     uint32_t *nvt_idx, bool *vo)
+{
+    uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
+    uint32_t cam = be32_to_cpu(qw1w2);
+
+    xive_os_cam_decode(cam, nvt_blk, nvt_idx, vo);
+    return qw1w2;
+}
+
+static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2)
+{
+    memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
+}
+
 static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr offset,
                                     unsigned size)
 {
-    uint32_t qw1w2_prev = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
     uint32_t qw1w2;
+    uint32_t qw1w2_new;
+    uint8_t nvt_blk;
+    uint32_t nvt_idx;
+    bool vo;
 
-    qw1w2 = xive_set_field32(TM_QW1W2_VO, qw1w2_prev, 0);
-    memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
+    qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo);
+
+    /* Invalidate CAM line */
+    qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0);
+    xive_tctx_set_os_cam(tctx, qw1w2_new);
     return qw1w2;
 }
 
-- 
2.21.0



  parent reply	other threads:[~2019-10-07  8:46 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-07  8:40 [PATCH 0/9] ppc/pnv: XIVE cleanup and fixes Cédric Le Goater
2019-10-07  8:40 ` [PATCH 1/9] ppc/pnv: Improve trigger data definition Cédric Le Goater
2019-10-14  5:28   ` David Gibson
2019-10-07  8:40 ` [PATCH 2/9] ppc/pnv: Use address_space_stq_be() when triggering an interrupt from PSI Cédric Le Goater
2019-10-14  5:30   ` David Gibson
2019-10-07  8:40 ` [PATCH 3/9] ppc/xive: Record the IPB in the associated NVT Cédric Le Goater
2019-10-14  5:32   ` David Gibson
2019-10-14  7:02     ` Cédric Le Goater
2019-10-07  8:40 ` [PATCH 4/9] ppc/xive: Introduce helpers for the NVT id Cédric Le Goater
2019-10-07  8:40 ` [PATCH 5/9] ppc/pnv: Remove pnv_xive_vst_size() routine Cédric Le Goater
2019-10-07  8:40 ` [PATCH 6/9] ppc/pnv: Dump the XIVE NVT table Cédric Le Goater
2019-10-07  8:41 ` [PATCH 7/9] ppc/pnv: Quiesce some XIVE errors Cédric Le Goater
2019-10-07  8:41 ` Cédric Le Goater [this message]
2019-10-07  8:41 ` [PATCH 9/9] ppc/xive: Check V bit in TM_PULL_POOL_CTX Cédric Le Goater
2019-10-21 12:58 ` [PATCH 0/9] ppc/pnv: XIVE cleanup and fixes Cédric Le Goater

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