qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: David Gibson <david@gibson.dropbear.id.au>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz <groug@kaod.org>
Subject: Re: [PATCH 1/9] ppc/pnv: Improve trigger data definition
Date: Mon, 14 Oct 2019 16:28:24 +1100	[thread overview]
Message-ID: <20191014052824.GS4080@umbus.fritz.box> (raw)
In-Reply-To: <20191007084102.29776-2-clg@kaod.org>

[-- Attachment #1: Type: text/plain, Size: 6354 bytes --]

On Mon, Oct 07, 2019 at 10:40:54AM +0200, Cédric Le Goater wrote:
> The trigger data is used for both triggers of a HW source interrupts,
> PHB, PSI, and triggers for rerouting interrupts between interrupt
> controllers.
> 
> When an interrupt is rerouted, the trigger data follows an "END
> trigger" format. In that case, the remote IC needs EAS containing an
> END index to perform a lookup of an END.
> 
> An END trigger, bit0 of word0 set to '1', is defined as :
> 
>              |0123|4567|0123|4567|0123|4567|0123|4567|
>     W0 E=1   |1P--|BLOC|          END IDX            |
>     W1 E=1   |M   |           END DATA               |
> 
> An EAS is defined as :
> 
>              |0123|4567|0123|4567|0123|4567|0123|4567|
>     W0       |V---|BLOC|          END IDX            |
>     W1       |M   |          END DATA                |
> 
> The END trigger adds an extra 'PQ' bit, bit1 of word0 set to '1',
> signaling that the PQ bits have been checked. That bit is unused in
> the initial EAS definition.
> 
> When a HW device performs the trigger, the trigger data follows an
> "EAS trigger" format because the trigger data in that case contains an
> EAS index which the IC needs to look for.
> 
> An EAS trigger, bit0 of word0 set to '0', is defined as :
> 
>              |0123|4567|0123|4567|0123|4567|0123|4567|
>     W0 E=0   |0P--|---- ---- ---- ---- ---- ---- ----|
>     W1 E=0   |BLOC|            EAS INDEX             |
> 
> There is also a 'PQ' bit, bit1 of word0 to '1', signaling that the
> PQ bits have been checked.
> 
> Introduce these new trigger bits and rename the XIVE_SRCNO macros in
> XIVE_EAS to reflect better the nature of the data.
> 
> Signed-off-by: Cédric Le Goater <clg@kaod.org>

Applied to ppc-for-4.2, thanks.

> ---
>  include/hw/ppc/xive_regs.h | 26 +++++++++++++++++++++++---
>  hw/intc/pnv_xive.c         | 20 ++++++++++++++++----
>  hw/intc/xive.c             |  4 ++--
>  3 files changed, 41 insertions(+), 9 deletions(-)
> 
> diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h
> index 08c8bf7172e2..55307cd1533c 100644
> --- a/include/hw/ppc/xive_regs.h
> +++ b/include/hw/ppc/xive_regs.h
> @@ -22,9 +22,29 @@
>  /*
>   * Interrupt source number encoding on PowerBUS
>   */
> -#define XIVE_SRCNO_BLOCK(srcno) (((srcno) >> 28) & 0xf)
> -#define XIVE_SRCNO_INDEX(srcno) ((srcno) & 0x0fffffff)
> -#define XIVE_SRCNO(blk, idx)    ((uint32_t)(blk) << 28 | (idx))
> +/*
> + * Trigger data definition
> + *
> + * The trigger definition is used for triggers both for HW source
> + * interrupts (PHB, PSI), as well as for rerouting interrupts between
> + * Interrupt Controller.
> + *
> + * HW source controllers set bit0 of word0 to ‘0’ as they provide EAS
> + * information (EAS block + EAS index) in the 8 byte data and not END
> + * information, which is use for rerouting interrupts.
> + *
> + * bit1 of word0 to ‘1’ signals that the state bit check has been
> + * performed.
> + */
> +#define XIVE_TRIGGER_END        PPC_BIT(0)
> +#define XIVE_TRIGGER_PQ         PPC_BIT(1)
> +
> +/*
> + * QEMU macros to manipulate the trigger payload in native endian
> + */
> +#define XIVE_EAS_BLOCK(n)       (((n) >> 28) & 0xf)
> +#define XIVE_EAS_INDEX(n)       ((n) & 0x0fffffff)
> +#define XIVE_EAS(blk, idx)      ((uint32_t)(blk) << 28 | (idx))
>  
>  #define TM_SHIFT                16
>  
> diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
> index ed6e9d71bbfa..348f2fdd263d 100644
> --- a/hw/intc/pnv_xive.c
> +++ b/hw/intc/pnv_xive.c
> @@ -385,7 +385,7 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx,
>      PnvXive *xive = PNV_XIVE(xrtr);
>  
>      if (pnv_xive_get_ic(blk) != xive) {
> -        xive_error(xive, "VST: EAS %x is remote !?", XIVE_SRCNO(blk, idx));
> +        xive_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx));
>          return -1;
>      }
>  
> @@ -431,7 +431,7 @@ static void pnv_xive_notify(XiveNotifier *xn, uint32_t srcno)
>      PnvXive *xive = PNV_XIVE(xn);
>      uint8_t blk = xive->chip->chip_id;
>  
> -    xive_router_notify(xn, XIVE_SRCNO(blk, srcno));
> +    xive_router_notify(xn, XIVE_EAS(blk, srcno));
>  }
>  
>  /*
> @@ -1225,12 +1225,24 @@ static const MemoryRegionOps pnv_xive_ic_reg_ops = {
>  
>  static void pnv_xive_ic_hw_trigger(PnvXive *xive, hwaddr addr, uint64_t val)
>  {
> +    uint8_t blk;
> +    uint32_t idx;
> +
> +    if (val & XIVE_TRIGGER_END) {
> +        xive_error(xive, "IC: END trigger at @0x%"HWADDR_PRIx" data 0x%"PRIx64,
> +                   addr, val);
> +        return;
> +    }
> +
>      /*
>       * Forward the source event notification directly to the Router.
>       * The source interrupt number should already be correctly encoded
>       * with the chip block id by the sending device (PHB, PSI).
>       */
> -    xive_router_notify(XIVE_NOTIFIER(xive), val);
> +    blk = XIVE_EAS_BLOCK(val);
> +    idx = XIVE_EAS_INDEX(val);
> +
> +    xive_router_notify(XIVE_NOTIFIER(xive), XIVE_EAS(blk, idx));
>  }
>  
>  static void pnv_xive_ic_notify_write(void *opaque, hwaddr addr, uint64_t val,
> @@ -1566,7 +1578,7 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon)
>  {
>      XiveRouter *xrtr = XIVE_ROUTER(xive);
>      uint8_t blk = xive->chip->chip_id;
> -    uint32_t srcno0 = XIVE_SRCNO(blk, 0);
> +    uint32_t srcno0 = XIVE_EAS(blk, 0);
>      uint32_t nr_ipis = pnv_xive_nr_ipis(xive);
>      uint32_t nr_ends = pnv_xive_nr_ends(xive);
>      XiveEAS eas;
> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> index 29df06df1136..cbe4ae6c294d 100644
> --- a/hw/intc/xive.c
> +++ b/hw/intc/xive.c
> @@ -1648,8 +1648,8 @@ do_escalation:
>  void xive_router_notify(XiveNotifier *xn, uint32_t lisn)
>  {
>      XiveRouter *xrtr = XIVE_ROUTER(xn);
> -    uint8_t eas_blk = XIVE_SRCNO_BLOCK(lisn);
> -    uint32_t eas_idx = XIVE_SRCNO_INDEX(lisn);
> +    uint8_t eas_blk = XIVE_EAS_BLOCK(lisn);
> +    uint32_t eas_idx = XIVE_EAS_INDEX(lisn);
>      XiveEAS eas;
>  
>      /* EAS cache lookup */

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

  reply	other threads:[~2019-10-14  6:03 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-07  8:40 [PATCH 0/9] ppc/pnv: XIVE cleanup and fixes Cédric Le Goater
2019-10-07  8:40 ` [PATCH 1/9] ppc/pnv: Improve trigger data definition Cédric Le Goater
2019-10-14  5:28   ` David Gibson [this message]
2019-10-07  8:40 ` [PATCH 2/9] ppc/pnv: Use address_space_stq_be() when triggering an interrupt from PSI Cédric Le Goater
2019-10-14  5:30   ` David Gibson
2019-10-07  8:40 ` [PATCH 3/9] ppc/xive: Record the IPB in the associated NVT Cédric Le Goater
2019-10-14  5:32   ` David Gibson
2019-10-14  7:02     ` Cédric Le Goater
2019-10-07  8:40 ` [PATCH 4/9] ppc/xive: Introduce helpers for the NVT id Cédric Le Goater
2019-10-07  8:40 ` [PATCH 5/9] ppc/pnv: Remove pnv_xive_vst_size() routine Cédric Le Goater
2019-10-07  8:40 ` [PATCH 6/9] ppc/pnv: Dump the XIVE NVT table Cédric Le Goater
2019-10-07  8:41 ` [PATCH 7/9] ppc/pnv: Quiesce some XIVE errors Cédric Le Goater
2019-10-07  8:41 ` [PATCH 8/9] ppc/xive: Introduce OS CAM line helpers Cédric Le Goater
2019-10-07  8:41 ` [PATCH 9/9] ppc/xive: Check V bit in TM_PULL_POOL_CTX Cédric Le Goater
2019-10-21 12:58 ` [PATCH 0/9] ppc/pnv: XIVE cleanup and fixes Cédric Le Goater

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20191014052824.GS4080@umbus.fritz.box \
    --to=david@gibson.dropbear.id.au \
    --cc=clg@kaod.org \
    --cc=groug@kaod.org \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).