From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 56/68] aspeed: Introduce an object class per SoC
Date: Mon, 14 Oct 2019 17:03:52 +0100 [thread overview]
Message-ID: <20191014160404.19553-57-peter.maydell@linaro.org> (raw)
In-Reply-To: <20191014160404.19553-1-peter.maydell@linaro.org>
From: Cédric Le Goater <clg@kaod.org>
It prepares ground for the AST2600.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20190925143248.10000-18-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/aspeed_soc.h | 9 +--
hw/arm/aspeed.c | 4 +-
hw/arm/aspeed_soc.c | 148 +++++++++++++++++++-----------------
3 files changed, 84 insertions(+), 77 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index b427f2668a8..667dfec0f7b 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -57,7 +57,9 @@ typedef struct AspeedSoCState {
#define TYPE_ASPEED_SOC "aspeed-soc"
#define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC)
-typedef struct AspeedSoCInfo {
+typedef struct AspeedSoCClass {
+ DeviceClass parent_class;
+
const char *name;
const char *cpu_type;
uint32_t silicon_rev;
@@ -67,11 +69,6 @@ typedef struct AspeedSoCInfo {
const int *irqmap;
const hwaddr *memmap;
uint32_t num_cpus;
-} AspeedSoCInfo;
-
-typedef struct AspeedSoCClass {
- DeviceClass parent_class;
- AspeedSoCInfo *info;
} AspeedSoCClass;
#define ASPEED_SOC_CLASS(klass) \
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 30e28048426..52993f84b46 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -215,7 +215,7 @@ static void aspeed_board_init(MachineState *machine,
memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
memory_region_add_subregion(&bmc->ram_container, 0, &bmc->ram);
memory_region_add_subregion(get_system_memory(),
- sc->info->memmap[ASPEED_SDRAM],
+ sc->memmap[ASPEED_SDRAM],
&bmc->ram_container);
max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
@@ -246,7 +246,7 @@ static void aspeed_board_init(MachineState *machine,
}
aspeed_board_binfo.ram_size = ram_size;
- aspeed_board_binfo.loader_start = sc->info->memmap[ASPEED_SDRAM];
+ aspeed_board_binfo.loader_start = sc->memmap[ASPEED_SDRAM];
aspeed_board_binfo.nb_cpus = bmc->soc.num_cpus;
if (cfg->i2c_init) {
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index e60f198d92c..a063be9fd79 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -115,35 +115,11 @@ static const int aspeed_soc_ast2400_irqmap[] = {
#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
-static const AspeedSoCInfo aspeed_socs[] = {
- {
- .name = "ast2400-a1",
- .cpu_type = ARM_CPU_TYPE_NAME("arm926"),
- .silicon_rev = AST2400_A1_SILICON_REV,
- .sram_size = 0x8000,
- .spis_num = 1,
- .wdts_num = 2,
- .irqmap = aspeed_soc_ast2400_irqmap,
- .memmap = aspeed_soc_ast2400_memmap,
- .num_cpus = 1,
- }, {
- .name = "ast2500-a1",
- .cpu_type = ARM_CPU_TYPE_NAME("arm1176"),
- .silicon_rev = AST2500_A1_SILICON_REV,
- .sram_size = 0x9000,
- .spis_num = 2,
- .wdts_num = 3,
- .irqmap = aspeed_soc_ast2500_irqmap,
- .memmap = aspeed_soc_ast2500_memmap,
- .num_cpus = 1,
- },
-};
-
static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
{
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- return qdev_get_gpio_in(DEVICE(&s->vic), sc->info->irqmap[ctrl]);
+ return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[ctrl]);
}
static void aspeed_soc_init(Object *obj)
@@ -154,13 +130,13 @@ static void aspeed_soc_init(Object *obj)
char socname[8];
char typename[64];
- if (sscanf(sc->info->name, "%7s", socname) != 1) {
+ if (sscanf(sc->name, "%7s", socname) != 1) {
g_assert_not_reached();
}
- for (i = 0; i < sc->info->num_cpus; i++) {
+ for (i = 0; i < sc->num_cpus; i++) {
object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
- sizeof(s->cpu[i]), sc->info->cpu_type,
+ sizeof(s->cpu[i]), sc->cpu_type,
&error_abort, NULL);
}
@@ -168,7 +144,7 @@ static void aspeed_soc_init(Object *obj)
sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
typename);
qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
- sc->info->silicon_rev);
+ sc->silicon_rev);
object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
"hw-strap1", &error_abort);
object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
@@ -200,7 +176,7 @@ static void aspeed_soc_init(Object *obj)
object_property_add_alias(obj, "dram", OBJECT(&s->fmc), "dram",
&error_abort);
- for (i = 0; i < sc->info->spis_num; i++) {
+ for (i = 0; i < sc->spis_num; i++) {
snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
sizeof(s->spi[i]), typename);
@@ -214,7 +190,7 @@ static void aspeed_soc_init(Object *obj)
object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
"max-ram-size", &error_abort);
- for (i = 0; i < sc->info->wdts_num; i++) {
+ for (i = 0; i < sc->wdts_num; i++) {
snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
sizeof(s->wdt[i]), typename);
@@ -252,13 +228,13 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
Error *err = NULL, *local_err = NULL;
/* IO space */
- create_unimplemented_device("aspeed_soc.io", sc->info->memmap[ASPEED_IOMEM],
+ create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM],
ASPEED_SOC_IOMEM_SIZE);
- if (s->num_cpus > sc->info->num_cpus) {
+ if (s->num_cpus > sc->num_cpus) {
warn_report("%s: invalid number of CPUs %d, using default %d",
- sc->info->name, s->num_cpus, sc->info->num_cpus);
- s->num_cpus = sc->info->num_cpus;
+ sc->name, s->num_cpus, sc->num_cpus);
+ s->num_cpus = sc->num_cpus;
}
/* CPU */
@@ -272,13 +248,13 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
/* SRAM */
memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
- sc->info->sram_size, &err);
+ sc->sram_size, &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(get_system_memory(),
- sc->info->memmap[ASPEED_SRAM], &s->sram);
+ sc->memmap[ASPEED_SRAM], &s->sram);
/* SCU */
object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
@@ -286,7 +262,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->info->memmap[ASPEED_SCU]);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);
/* VIC */
object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
@@ -294,7 +270,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->info->memmap[ASPEED_VIC]);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_VIC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
@@ -306,7 +282,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->info->memmap[ASPEED_RTC]);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
aspeed_soc_get_irq(s, ASPEED_RTC));
@@ -317,7 +293,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
- sc->info->memmap[ASPEED_TIMER1]);
+ sc->memmap[ASPEED_TIMER1]);
for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
@@ -326,7 +302,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
/* UART - attach an 8250 to the IO space as our UART5 */
if (serial_hd(0)) {
qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
- serial_mm_init(get_system_memory(), sc->info->memmap[ASPEED_UART5], 2,
+ serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2,
uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
}
@@ -336,12 +312,12 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->info->memmap[ASPEED_I2C]);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
aspeed_soc_get_irq(s, ASPEED_I2C));
/* FMC, The number of CS is set at the board level */
- object_property_set_int(OBJECT(&s->fmc), sc->info->memmap[ASPEED_SDRAM],
+ object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM],
"sdram-base", &err);
if (err) {
error_propagate(errp, err);
@@ -352,14 +328,14 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->info->memmap[ASPEED_FMC]);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
s->fmc.ctrl->flash_window_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
aspeed_soc_get_irq(s, ASPEED_FMC));
/* SPI */
- for (i = 0; i < sc->info->spis_num; i++) {
+ for (i = 0; i < sc->spis_num; i++) {
object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
&local_err);
@@ -369,7 +345,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
- sc->info->memmap[ASPEED_SPI1 + i]);
+ sc->memmap[ASPEED_SPI1 + i]);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
s->spi[i].ctrl->flash_window_base);
}
@@ -380,10 +356,10 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->info->memmap[ASPEED_SDMC]);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]);
/* Watch dog */
- for (i = 0; i < sc->info->wdts_num; i++) {
+ for (i = 0; i < sc->wdts_num; i++) {
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
@@ -392,7 +368,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
- sc->info->memmap[ASPEED_WDT] + i * awc->offset);
+ sc->memmap[ASPEED_WDT] + i * awc->offset);
}
/* Net */
@@ -408,7 +384,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
- sc->info->memmap[ASPEED_ETH1 + i]);
+ sc->memmap[ASPEED_ETH1 + i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
}
@@ -420,7 +396,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
- sc->info->memmap[ASPEED_XDMA]);
+ sc->memmap[ASPEED_XDMA]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
aspeed_soc_get_irq(s, ASPEED_XDMA));
@@ -430,7 +406,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->info->memmap[ASPEED_GPIO]);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
aspeed_soc_get_irq(s, ASPEED_GPIO));
@@ -441,7 +417,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
- sc->info->memmap[ASPEED_SDHCI]);
+ sc->memmap[ASPEED_SDHCI]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
aspeed_soc_get_irq(s, ASPEED_SDHCI));
}
@@ -453,9 +429,7 @@ static Property aspeed_soc_properties[] = {
static void aspeed_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
- AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
- sc->info = (AspeedSoCInfo *) data;
dc->realize = aspeed_soc_realize;
/* Reason: Uses serial_hds and nd_table in realize() directly */
dc->user_creatable = false;
@@ -465,26 +439,62 @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo aspeed_soc_type_info = {
.name = TYPE_ASPEED_SOC,
.parent = TYPE_DEVICE,
- .instance_init = aspeed_soc_init,
.instance_size = sizeof(AspeedSoCState),
.class_size = sizeof(AspeedSoCClass),
+ .class_init = aspeed_soc_class_init,
.abstract = true,
};
-static void aspeed_soc_register_types(void)
+static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
{
- int i;
+ AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
- type_register_static(&aspeed_soc_type_info);
- for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) {
- TypeInfo ti = {
- .name = aspeed_socs[i].name,
- .parent = TYPE_ASPEED_SOC,
- .class_init = aspeed_soc_class_init,
- .class_data = (void *) &aspeed_socs[i],
- };
- type_register(&ti);
- }
+ sc->name = "ast2400-a1";
+ sc->cpu_type = ARM_CPU_TYPE_NAME("arm926");
+ sc->silicon_rev = AST2400_A1_SILICON_REV;
+ sc->sram_size = 0x8000;
+ sc->spis_num = 1;
+ sc->wdts_num = 2;
+ sc->irqmap = aspeed_soc_ast2400_irqmap;
+ sc->memmap = aspeed_soc_ast2400_memmap;
+ sc->num_cpus = 1;
}
+static const TypeInfo aspeed_soc_ast2400_type_info = {
+ .name = "ast2400-a1",
+ .parent = TYPE_ASPEED_SOC,
+ .instance_init = aspeed_soc_init,
+ .instance_size = sizeof(AspeedSoCState),
+ .class_init = aspeed_soc_ast2400_class_init,
+};
+
+static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
+{
+ AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
+
+ sc->name = "ast2500-a1";
+ sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
+ sc->silicon_rev = AST2500_A1_SILICON_REV;
+ sc->sram_size = 0x9000;
+ sc->spis_num = 2;
+ sc->wdts_num = 3;
+ sc->irqmap = aspeed_soc_ast2500_irqmap;
+ sc->memmap = aspeed_soc_ast2500_memmap;
+ sc->num_cpus = 1;
+}
+
+static const TypeInfo aspeed_soc_ast2500_type_info = {
+ .name = "ast2500-a1",
+ .parent = TYPE_ASPEED_SOC,
+ .instance_init = aspeed_soc_init,
+ .instance_size = sizeof(AspeedSoCState),
+ .class_init = aspeed_soc_ast2500_class_init,
+};
+static void aspeed_soc_register_types(void)
+{
+ type_register_static(&aspeed_soc_type_info);
+ type_register_static(&aspeed_soc_ast2400_type_info);
+ type_register_static(&aspeed_soc_ast2500_type_info);
+};
+
type_init(aspeed_soc_register_types)
--
2.20.1
next prev parent reply other threads:[~2019-10-14 16:48 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-14 16:02 [PULL 00/68] target-arm queue Peter Maydell
2019-10-14 16:02 ` [PULL 01/68] linux headers: update against v5.4-rc1 Peter Maydell
2019-10-14 16:02 ` [PULL 02/68] intc/arm_gic: Support IRQ injection for more than 256 vpus Peter Maydell
2019-10-14 16:02 ` [PULL 03/68] ARM: KVM: Check KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 for smp_cpus > 256 Peter Maydell
2019-10-14 16:03 ` [PULL 04/68] ptimer: Rename ptimer_init() to ptimer_init_with_bh() Peter Maydell
2019-10-14 16:03 ` [PULL 05/68] ptimer: Provide new transaction-based API Peter Maydell
2019-10-14 16:03 ` [PULL 06/68] tests/ptimer-test: Switch to transaction-based ptimer API Peter Maydell
2019-10-14 16:03 ` [PULL 07/68] hw/timer/arm_timer.c: " Peter Maydell
2019-10-14 16:03 ` [PULL 08/68] hw/arm/musicpal.c: " Peter Maydell
2019-10-14 16:03 ` [PULL 09/68] hw/timer/allwinner-a10-pit.c: " Peter Maydell
2019-10-14 16:03 ` [PULL 10/68] hw/timer/arm_mptimer.c: " Peter Maydell
2019-10-14 16:03 ` [PULL 11/68] hw/timer/cmsdk-apb-dualtimer.c: " Peter Maydell
2019-10-14 16:03 ` [PULL 12/68] hw/timer/cmsdk-apb-timer.c: " Peter Maydell
2019-10-14 16:03 ` [PULL 13/68] hw/timer/digic-timer.c: " Peter Maydell
2019-10-14 16:03 ` [PULL 14/68] hw/timer/exynos4210_mct.c: Switch GFRC " Peter Maydell
2019-10-14 16:03 ` [PULL 15/68] hw/timer/exynos4210_mct.c: Switch LFRC " Peter Maydell
2019-10-14 16:03 ` [PULL 16/68] hw/timer/exynos4210_mct.c: Switch ltick " Peter Maydell
2019-10-14 16:03 ` [PULL 17/68] hw/timer/exynos4210_pwm.c: Switch " Peter Maydell
2019-10-14 16:03 ` [PULL 18/68] hw/timer/exynos4210_rtc.c: Switch 1Hz ptimer to transaction-based API Peter Maydell
2019-10-14 16:03 ` [PULL 19/68] hw/timer/exynos4210_rtc.c: Switch main " Peter Maydell
2019-10-14 16:03 ` [PULL 20/68] hw/timer/imx_epit.c: Switch to transaction-based ptimer API Peter Maydell
2019-10-14 16:03 ` [PULL 21/68] hw/timer/imx_gpt.c: " Peter Maydell
2019-10-14 16:03 ` [PULL 22/68] hw/timer/mss-timerc: " Peter Maydell
2019-10-14 16:03 ` [PULL 23/68] hw/watchdog/cmsdk-apb-watchdog.c: " Peter Maydell
2019-10-14 16:03 ` [PULL 24/68] hw/net/lan9118.c: " Peter Maydell
2019-10-14 16:03 ` [PULL 25/68] target/arm/arm-semi: Capture errno in softmmu version of set_swi_errno() Peter Maydell
2019-10-14 16:03 ` [PULL 26/68] target/arm/arm-semi: Always set some kind of errno for failed calls Peter Maydell
2019-10-14 16:03 ` [PULL 27/68] target/arm/arm-semi: Correct comment about gdb syscall races Peter Maydell
2019-10-14 16:03 ` [PULL 28/68] target/arm/arm-semi: Make semihosting code hand out its own file descriptors Peter Maydell
2019-10-14 16:03 ` [PULL 29/68] target/arm/arm-semi: Restrict use of TaskState* Peter Maydell
2019-10-14 16:03 ` [PULL 30/68] target/arm/arm-semi: Use set_swi_errno() in gdbstub callback functions Peter Maydell
2019-10-14 16:03 ` [PULL 31/68] target/arm/arm-semi: Factor out implementation of SYS_CLOSE Peter Maydell
2019-10-14 16:03 ` [PULL 32/68] target/arm/arm-semi: Factor out implementation of SYS_WRITE Peter Maydell
2019-10-14 16:03 ` [PULL 33/68] target/arm/arm-semi: Factor out implementation of SYS_READ Peter Maydell
2019-10-14 16:03 ` [PULL 34/68] target/arm/arm-semi: Factor out implementation of SYS_ISTTY Peter Maydell
2019-10-14 16:03 ` [PULL 35/68] target/arm/arm-semi: Factor out implementation of SYS_SEEK Peter Maydell
2019-10-14 16:03 ` [PULL 36/68] target/arm/arm-semi: Factor out implementation of SYS_FLEN Peter Maydell
2019-10-14 16:03 ` [PULL 37/68] target/arm/arm-semi: Implement support for semihosting feature detection Peter Maydell
2019-10-14 16:03 ` [PULL 38/68] target/arm/arm-semi: Implement SH_EXT_EXIT_EXTENDED extension Peter Maydell
2019-10-14 16:03 ` [PULL 39/68] target/arm/arm-semi: Implement SH_EXT_STDOUT_STDERR extension Peter Maydell
2019-10-14 16:03 ` [PULL 40/68] aspeed/wdt: Check correct register for clock source Peter Maydell
2019-10-14 16:03 ` [PULL 41/68] hw/sd/aspeed_sdhci: New device Peter Maydell
2019-10-14 16:03 ` [PULL 42/68] hw: aspeed_scu: Add AST2600 support Peter Maydell
2019-10-14 16:03 ` [PULL 43/68] aspeed/timer: Introduce an object class per SoC Peter Maydell
2019-10-14 16:03 ` [PULL 44/68] aspeed/timer: Add support for control register 3 Peter Maydell
2019-10-14 16:03 ` [PULL 45/68] aspeed/timer: Add AST2600 support Peter Maydell
2019-10-14 16:03 ` [PULL 46/68] aspeed/timer: Add support for IRQ status register on the AST2600 Peter Maydell
2019-10-14 16:03 ` [PULL 47/68] aspeed/sdmc: Introduce an object class per SoC Peter Maydell
2019-10-14 16:03 ` [PULL 48/68] aspeed/sdmc: Add AST2600 support Peter Maydell
2019-10-14 16:03 ` [PULL 49/68] watchdog/aspeed: Introduce an object class per SoC Peter Maydell
2019-10-14 16:03 ` [PULL 50/68] hw: wdt_aspeed: Add AST2600 support Peter Maydell
2019-10-14 16:03 ` [PULL 51/68] aspeed/smc: Introduce segment operations Peter Maydell
2019-10-14 16:03 ` [PULL 52/68] aspeed/smc: Add AST2600 support Peter Maydell
2019-10-14 16:03 ` [PULL 53/68] hw/gpio: Add in AST2600 specific implementation Peter Maydell
2019-10-14 16:03 ` [PULL 54/68] aspeed/i2c: Introduce an object class per SoC Peter Maydell
2019-10-14 16:03 ` [PULL 55/68] aspeed/i2c: Add AST2600 support Peter Maydell
2019-10-14 16:03 ` Peter Maydell [this message]
2019-10-14 16:03 ` [PULL 57/68] aspeed/soc: " Peter Maydell
2019-10-14 16:03 ` [PULL 58/68] m25p80: Add support for w25q512jv Peter Maydell
2019-10-14 16:03 ` [PULL 59/68] aspeed: Add an AST2600 eval board Peter Maydell
2019-10-15 17:03 ` Peter Maydell
2019-10-15 17:43 ` Cédric Le Goater
2019-10-15 17:55 ` Peter Maydell
2019-10-16 11:28 ` Joel Stanley
2019-10-16 12:20 ` Philippe Mathieu-Daudé
2019-10-16 12:41 ` Cédric Le Goater
2019-10-16 12:44 ` Philippe Mathieu-Daudé
2019-10-14 16:03 ` [PULL 60/68] aspeed: Parameterise number of MACs Peter Maydell
2019-10-14 16:03 ` [PULL 61/68] aspeed: add support for the Aspeed MII controller of the AST2600 Peter Maydell
2019-10-14 16:03 ` [PULL 62/68] aspeed/soc: Add ASPEED Video stub Peter Maydell
2019-10-14 16:03 ` [PULL 63/68] hw/arm/raspi: Use the IEC binary prefix definitions Peter Maydell
2019-10-14 16:04 ` [PULL 64/68] hw/arm/bcm2835_peripherals: Improve logging Peter Maydell
2019-10-14 16:04 ` [PULL 65/68] hw/arm/bcm2835_peripherals: Name various address spaces Peter Maydell
2019-10-14 16:04 ` [PULL 66/68] hw/arm/bcm2835: Rename some definitions Peter Maydell
2019-10-14 16:04 ` [PULL 67/68] hw/arm/bcm2835: Add various unimplemented peripherals Peter Maydell
2019-10-14 16:04 ` [PULL 68/68] hw/misc/bcm2835_mbox: Add trace events Peter Maydell
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