From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: elver@google.com, icb@rice.edu, qemu-arm@nongnu.org
Subject: [PATCH v3 3/3] tests/tcg/aarch64: Add mte smoke tests
Date: Tue, 15 Oct 2019 09:35:07 -0700 [thread overview]
Message-ID: <20191015163507.12153-4-richard.henderson@linaro.org> (raw)
In-Reply-To: <20191015163507.12153-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tests/tcg/aarch64/mte-1.c | 27 +++++++++++++++++++++
tests/tcg/aarch64/mte-2.c | 39 +++++++++++++++++++++++++++++++
tests/tcg/aarch64/Makefile.target | 5 ++++
3 files changed, 71 insertions(+)
create mode 100644 tests/tcg/aarch64/mte-1.c
create mode 100644 tests/tcg/aarch64/mte-2.c
diff --git a/tests/tcg/aarch64/mte-1.c b/tests/tcg/aarch64/mte-1.c
new file mode 100644
index 0000000000..18bfb1120f
--- /dev/null
+++ b/tests/tcg/aarch64/mte-1.c
@@ -0,0 +1,27 @@
+/*
+ * Memory tagging, basic pass cases.
+ */
+
+#include <assert.h>
+
+asm(".arch armv8.5-a+memtag");
+
+int data[16 / sizeof(int)] __attribute__((aligned(16)));
+
+int main(int ac, char **av)
+{
+ int *p0 = data;
+ int *p1, *p2;
+ long c;
+
+ asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(1));
+ assert(p1 != p0);
+ asm("subp %0,%1,%2" : "=r"(c) : "r"(p0), "r"(p1));
+ assert(c == 0);
+
+ asm("stg %0, [%0]" : : "r"(p1));
+ asm("ldg %0, [%1]" : "=r"(p2) : "r"(p0), "0"(p0));
+ assert(p1 == p2);
+
+ return 0;
+}
diff --git a/tests/tcg/aarch64/mte-2.c b/tests/tcg/aarch64/mte-2.c
new file mode 100644
index 0000000000..2991b7df69
--- /dev/null
+++ b/tests/tcg/aarch64/mte-2.c
@@ -0,0 +1,39 @@
+/*
+ * Memory tagging, basic fail cases.
+ */
+
+#include <assert.h>
+#include <signal.h>
+#include <stdlib.h>
+
+asm(".arch armv8.5-a+memtag");
+
+int data[16 / sizeof(int)] __attribute__((aligned(16)));
+
+void pass(int sig)
+{
+ exit(0);
+}
+
+int main(int ac, char **av)
+{
+ int *p0 = data;
+ int *p1, *p2;
+ long excl = 1;
+
+ /* Create two differently tagged pointers. */
+ asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl));
+ asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1));
+ assert(excl != 1);
+ asm("irg %0,%1,%2" : "=r"(p2) : "r"(p0), "r"(excl));
+ assert(p1 != p2);
+
+ /* Store the tag from the first pointer. */
+ asm("stg %0, [%0]" : : "r"(p1));
+
+ *p1 = 0;
+ signal(SIGSEGV, pass);
+ *p2 = 0;
+
+ assert(0);
+}
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index 0040b68dd0..0971c244b7 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -32,4 +32,9 @@ run-semihosting: semihosting
# AARCH64_TESTS += bti-1
bti-1: LDFLAGS += -nostdlib -Wl,-T,$(AARCH64_SRC)/bti.ld
+# We need binutils-2.32 to assemble this test case.
+# AARCH64_TESTS += mte-1 mte-2
+mte-%: CFLAGS += -O -g
+run-mte-%: QEMU += -cpu max,x-tagged-pages=on
+
TESTS += $(AARCH64_TESTS)
--
2.17.1
next prev parent reply other threads:[~2019-10-15 16:57 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-15 16:35 [PATCH 0/3] target/arm: Implement ARMv8.5-MemTag, user mode Richard Henderson
2019-10-15 16:35 ` [PATCH v3 1/3] tcg: Introduce target-specific page data for user-only Richard Henderson
2019-10-15 16:35 ` [PATCH v3 2/3] target/arm: Add allocation tag storage for user mode Richard Henderson
2019-10-15 16:35 ` Richard Henderson [this message]
2019-12-06 13:23 ` [PATCH 0/3] target/arm: Implement ARMv8.5-MemTag, " Peter Maydell
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