From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: robert.foley@futurewei.com, "Riku Voipio" <riku.voipio@iki.fi>,
"Richard Henderson" <richard.henderson@linaro.org>,
peter.puhov@futurewei.com, aaron@os.amperecomputing.com,
cota@braap.org, "Paolo Bonzini" <pbonzini@redhat.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Richard Henderson" <rth@twiddle.net>
Subject: [PATCH v6 14/54] atomic_template: add inline trace/plugin helpers
Date: Thu, 17 Oct 2019 14:15:35 +0100 [thread overview]
Message-ID: <20191017131615.19660-15-alex.bennee@linaro.org> (raw)
In-Reply-To: <20191017131615.19660-1-alex.bennee@linaro.org>
From: "Emilio G. Cota" <cota@braap.org>
In preparation for plugin support.
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
v4
- move common stuff to atomic_common.inc.c
- fix ups for widened uint16_t info
- drop haddr in helpers
- fix wide lines
v6
- rebase fixes
---
accel/tcg/atomic_common.inc.c | 50 ++++++++++++++++++
accel/tcg/atomic_template.h | 96 +++++++++++++++++++++--------------
accel/tcg/cputlb.c | 2 +
accel/tcg/user-exec.c | 2 +
4 files changed, 111 insertions(+), 39 deletions(-)
create mode 100644 accel/tcg/atomic_common.inc.c
diff --git a/accel/tcg/atomic_common.inc.c b/accel/tcg/atomic_common.inc.c
new file mode 100644
index 0000000000..a86098fb2d
--- /dev/null
+++ b/accel/tcg/atomic_common.inc.c
@@ -0,0 +1,50 @@
+/*
+ * Common Atomic Helper Functions
+ *
+ * This file should be included before the various instantiations of
+ * the atomic_template.h helpers.
+ *
+ * Copyright (c) 2019 Linaro
+ * Written by Alex Bennée <alex.bennee@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+static inline
+void atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+ CPUState *cpu = env_cpu(env);
+
+ trace_guest_mem_before_exec(cpu, addr, info);
+ trace_guest_mem_before_exec(cpu, addr, info | TRACE_MEM_ST);
+}
+
+static inline void
+atomic_trace_rmw_post(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+}
+
+static inline
+void atomic_trace_ld_pre(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+ trace_guest_mem_before_exec(env_cpu(env), addr, info);
+}
+
+static inline
+void atomic_trace_ld_post(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+}
+
+static inline
+void atomic_trace_st_pre(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+ trace_guest_mem_before_exec(env_cpu(env), addr, info);
+}
+
+static inline
+void atomic_trace_st_post(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+}
diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h
index 473d7e5a94..84d3370bf0 100644
--- a/accel/tcg/atomic_template.h
+++ b/accel/tcg/atomic_template.h
@@ -59,29 +59,6 @@
# define ABI_TYPE uint32_t
#endif
-#define ATOMIC_TRACE_RMW do { \
- uint16_t info = glue(trace_mem_build_info_no_se, MEND) \
- (SHIFT, false, ATOMIC_MMU_IDX); \
- \
- trace_guest_mem_before_exec(env_cpu(env), addr, info); \
- trace_guest_mem_before_exec(env_cpu(env), addr, \
- info | TRACE_MEM_ST); \
- } while (0)
-
-#define ATOMIC_TRACE_LD do { \
- uint16_t info = glue(trace_mem_build_info_no_se, MEND) \
- (SHIFT, false, ATOMIC_MMU_IDX); \
- \
- trace_guest_mem_before_exec(env_cpu(env), addr, info); \
- } while (0)
-
-#define ATOMIC_TRACE_ST do { \
- uint16_t info = glue(trace_mem_build_info_no_se, MEND) \
- (SHIFT, true, ATOMIC_MMU_IDX); \
- \
- trace_guest_mem_before_exec(env_cpu(env), addr, info); \
- } while (0)
-
/* Define host-endian atomic operations. Note that END is used within
the ATOMIC_NAME macro, and redefined below. */
#if DATA_SIZE == 1
@@ -101,14 +78,17 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
ATOMIC_MMU_DECLS;
DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
DATA_TYPE ret;
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, false,
+ ATOMIC_MMU_IDX);
- ATOMIC_TRACE_RMW;
+ atomic_trace_rmw_pre(env, addr, info);
#if DATA_SIZE == 16
ret = atomic16_cmpxchg(haddr, cmpv, newv);
#else
ret = atomic_cmpxchg__nocheck(haddr, cmpv, newv);
#endif
ATOMIC_MMU_CLEANUP;
+ atomic_trace_rmw_post(env, addr, info);
return ret;
}
@@ -118,10 +98,13 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr EXTRA_ARGS)
{
ATOMIC_MMU_DECLS;
DATA_TYPE val, *haddr = ATOMIC_MMU_LOOKUP;
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, false,
+ ATOMIC_MMU_IDX);
- ATOMIC_TRACE_LD;
+ atomic_trace_ld_pre(env, addr, info);
val = atomic16_read(haddr);
ATOMIC_MMU_CLEANUP;
+ atomic_trace_ld_post(env, addr, info);
return val;
}
@@ -130,10 +113,13 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr,
{
ATOMIC_MMU_DECLS;
DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, true,
+ ATOMIC_MMU_IDX);
- ATOMIC_TRACE_ST;
+ atomic_trace_st_pre(env, addr, info);
atomic16_set(haddr, val);
ATOMIC_MMU_CLEANUP;
+ atomic_trace_st_post(env, addr, info);
}
#endif
#else
@@ -143,10 +129,13 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr,
ATOMIC_MMU_DECLS;
DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
DATA_TYPE ret;
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, false,
+ ATOMIC_MMU_IDX);
- ATOMIC_TRACE_RMW;
+ atomic_trace_rmw_pre(env, addr, info);
ret = atomic_xchg__nocheck(haddr, val);
ATOMIC_MMU_CLEANUP;
+ atomic_trace_rmw_post(env, addr, info);
return ret;
}
@@ -157,10 +146,14 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
ATOMIC_MMU_DECLS; \
DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; \
DATA_TYPE ret; \
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, \
+ false, \
+ ATOMIC_MMU_IDX); \
\
- ATOMIC_TRACE_RMW; \
+ atomic_trace_rmw_pre(env, addr, info); \
ret = atomic_##X(haddr, val); \
ATOMIC_MMU_CLEANUP; \
+ atomic_trace_rmw_post(env, addr, info); \
return ret; \
}
@@ -189,8 +182,11 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
ATOMIC_MMU_DECLS; \
XDATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; \
XDATA_TYPE cmp, old, new, val = xval; \
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, \
+ false, \
+ ATOMIC_MMU_IDX); \
\
- ATOMIC_TRACE_RMW; \
+ atomic_trace_rmw_pre(env, addr, info); \
smp_mb(); \
cmp = atomic_read__nocheck(haddr); \
do { \
@@ -198,6 +194,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
cmp = atomic_cmpxchg__nocheck(haddr, old, new); \
} while (cmp != old); \
ATOMIC_MMU_CLEANUP; \
+ atomic_trace_rmw_post(env, addr, info); \
return RET; \
}
@@ -235,14 +232,18 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
ATOMIC_MMU_DECLS;
DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
DATA_TYPE ret;
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,
+ false,
+ ATOMIC_MMU_IDX);
- ATOMIC_TRACE_RMW;
+ atomic_trace_rmw_pre(env, addr, info);
#if DATA_SIZE == 16
ret = atomic16_cmpxchg(haddr, BSWAP(cmpv), BSWAP(newv));
#else
ret = atomic_cmpxchg__nocheck(haddr, BSWAP(cmpv), BSWAP(newv));
#endif
ATOMIC_MMU_CLEANUP;
+ atomic_trace_rmw_post(env, addr, info);
return BSWAP(ret);
}
@@ -252,10 +253,14 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr EXTRA_ARGS)
{
ATOMIC_MMU_DECLS;
DATA_TYPE val, *haddr = ATOMIC_MMU_LOOKUP;
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,
+ false,
+ ATOMIC_MMU_IDX);
- ATOMIC_TRACE_LD;
+ atomic_trace_ld_pre(env, addr, info);
val = atomic16_read(haddr);
ATOMIC_MMU_CLEANUP;
+ atomic_trace_ld_post(env, addr, info);
return BSWAP(val);
}
@@ -264,11 +269,16 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr,
{
ATOMIC_MMU_DECLS;
DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,
+ true,
+ ATOMIC_MMU_IDX);
- ATOMIC_TRACE_ST;
+ val = BSWAP(val);
+ atomic_trace_st_pre(env, addr, info);
val = BSWAP(val);
atomic16_set(haddr, val);
ATOMIC_MMU_CLEANUP;
+ atomic_trace_st_post(env, addr, info);
}
#endif
#else
@@ -278,10 +288,14 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr,
ATOMIC_MMU_DECLS;
DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
ABI_TYPE ret;
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,
+ false,
+ ATOMIC_MMU_IDX);
- ATOMIC_TRACE_RMW;
+ atomic_trace_rmw_pre(env, addr, info);
ret = atomic_xchg__nocheck(haddr, BSWAP(val));
ATOMIC_MMU_CLEANUP;
+ atomic_trace_rmw_post(env, addr, info);
return BSWAP(ret);
}
@@ -292,10 +306,14 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
ATOMIC_MMU_DECLS; \
DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; \
DATA_TYPE ret; \
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, \
+ false, \
+ ATOMIC_MMU_IDX); \
\
- ATOMIC_TRACE_RMW; \
+ atomic_trace_rmw_pre(env, addr, info); \
ret = atomic_##X(haddr, BSWAP(val)); \
ATOMIC_MMU_CLEANUP; \
+ atomic_trace_rmw_post(env, addr, info); \
return BSWAP(ret); \
}
@@ -322,8 +340,11 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
ATOMIC_MMU_DECLS; \
XDATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; \
XDATA_TYPE ldo, ldn, old, new, val = xval; \
+ uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, \
+ false, \
+ ATOMIC_MMU_IDX); \
\
- ATOMIC_TRACE_RMW; \
+ atomic_trace_rmw_pre(env, addr, info); \
smp_mb(); \
ldn = atomic_read__nocheck(haddr); \
do { \
@@ -331,6 +352,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
ldn = atomic_cmpxchg__nocheck(haddr, ldo, BSWAP(new)); \
} while (ldo != ldn); \
ATOMIC_MMU_CLEANUP; \
+ atomic_trace_rmw_post(env, addr, info); \
return RET; \
}
@@ -358,10 +380,6 @@ GEN_ATOMIC_HELPER_FN(add_fetch, ADD, DATA_TYPE, new)
#undef MEND
#endif /* DATA_SIZE > 1 */
-#undef ATOMIC_TRACE_ST
-#undef ATOMIC_TRACE_LD
-#undef ATOMIC_TRACE_RMW
-
#undef BSWAP
#undef ABI_TYPE
#undef DATA_TYPE
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 82a5783a2b..82282d30d9 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1825,6 +1825,8 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
#define ATOMIC_MMU_CLEANUP
#define ATOMIC_MMU_IDX get_mmuidx(oi)
+#include "atomic_common.inc.c"
+
#define DATA_SIZE 1
#include "atomic_template.h"
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 8d315a6587..b09f7a1577 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -756,6 +756,8 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
#define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END))
#define EXTRA_ARGS
+#include "atomic_common.inc.c"
+
#define DATA_SIZE 1
#include "atomic_template.h"
--
2.20.1
next prev parent reply other threads:[~2019-10-17 14:16 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-17 13:15 [PATCH for 4.2 v6 00/54] Support for TCG plugins Alex Bennée
2019-10-17 13:15 ` [PATCH v6 01/54] trace: expand mem_info:size_shift to 4 bits Alex Bennée
2019-10-17 13:15 ` [PATCH v6 02/54] trace: add mmu_index to mem_info Alex Bennée
2019-10-17 13:15 ` [PATCH v6 03/54] cpu: introduce cpu_in_exclusive_context() Alex Bennée
2019-10-17 13:15 ` [PATCH v6 04/54] translate-all: use cpu_in_exclusive_work_context() in tb_flush Alex Bennée
2019-10-17 13:15 ` [PATCH v6 05/54] docs/devel: add plugins.rst design document Alex Bennée
2019-10-17 13:15 ` [PATCH v6 06/54] plugin: add user-facing API Alex Bennée
2019-10-17 13:15 ` [PATCH v6 07/54] plugin: add core code Alex Bennée
2019-10-17 13:15 ` [PATCH v6 08/54] plugin: add implementation of the api Alex Bennée
2019-10-17 13:15 ` [PATCH v6 09/54] queue: add QTAILQ_REMOVE_SEVERAL Alex Bennée
2019-10-17 13:15 ` [PATCH v6 10/54] cputlb: document get_page_addr_code Alex Bennée
2019-10-17 13:15 ` [PATCH v6 11/54] cputlb: introduce get_page_addr_code_hostp Alex Bennée
2019-10-17 13:15 ` [PATCH v6 12/54] tcg: add tcg_gen_st_ptr Alex Bennée
2019-10-17 13:15 ` [PATCH v6 13/54] plugin-gen: add module for TCG-related code Alex Bennée
2019-10-17 13:15 ` Alex Bennée [this message]
2019-10-17 13:15 ` [PATCH v6 15/54] tcg: let plugins instrument virtual memory accesses Alex Bennée
2019-10-17 13:15 ` [PATCH v6 16/54] plugins: implement helpers for resolving hwaddr Alex Bennée
2019-10-17 13:15 ` [PATCH v6 17/54] translate-all: notify plugin code of tb_flush Alex Bennée
2019-10-17 13:15 ` [PATCH v6 18/54] *-user: notify plugin of exit Alex Bennée
2019-10-17 13:15 ` [PATCH v6 19/54] *-user: plugin syscalls Alex Bennée
2019-10-17 13:15 ` [PATCH v6 20/54] cpu: hook plugin vcpu events Alex Bennée
2019-10-17 13:15 ` [PATCH v6 21/54] plugin-gen: add plugin_insn_append Alex Bennée
2019-10-17 13:15 ` [PATCH v6 22/54] translator: add translator_ld{ub,sw,uw,l,q} Alex Bennée
2019-10-17 13:15 ` [PATCH v6 23/54] target/arm: fetch code with translator_ld Alex Bennée
2019-10-17 13:15 ` [PATCH v6 24/54] target/ppc: " Alex Bennée
2019-10-17 13:15 ` [PATCH v6 25/54] target/sh4: " Alex Bennée
2019-10-17 13:15 ` [PATCH v6 26/54] target/i386: " Alex Bennée
2019-10-17 13:15 ` [PATCH v6 27/54] target/hppa: " Alex Bennée
2019-10-17 13:15 ` [PATCH v6 28/54] target/m68k: " Alex Bennée
2019-10-17 13:15 ` [PATCH v6 29/54] target/alpha: " Alex Bennée
2019-10-17 13:15 ` [PATCH v6 30/54] target/riscv: " Alex Bennée
2019-10-17 13:15 ` [PATCH v6 31/54] target/sparc: " Alex Bennée
2019-10-17 13:15 ` [PATCH v6 32/54] target/xtensa: " Alex Bennée
2019-10-17 13:15 ` [PATCH v6 33/54] target/openrisc: " Alex Bennée
2019-10-17 13:15 ` [PATCH v6 34/54] translator: inject instrumentation from plugins Alex Bennée
2019-10-17 13:15 ` [PATCH v6 35/54] configure: add --enable-plugins Alex Bennée
2019-10-17 13:15 ` [PATCH v6 36/54] plugin: add API symbols to qemu-plugins.symbols Alex Bennée
2019-10-17 13:15 ` [PATCH v6 37/54] plugin: expand the plugin_init function to include an info block Alex Bennée
2019-10-18 15:32 ` Aaron Lindsay OS
2019-10-18 15:54 ` Alex Bennée
2019-10-22 14:04 ` Aaron Lindsay OS
2019-10-24 13:09 ` Alex Bennée
2019-10-17 13:15 ` [PATCH v6 38/54] plugin: add qemu_plugin_insn_disas helper Alex Bennée
2019-10-17 13:16 ` [PATCH v6 39/54] plugin: add qemu_plugin_outs helper Alex Bennée
2019-10-22 14:07 ` Aaron Lindsay OS
2019-10-17 13:16 ` [PATCH v6 40/54] vl: support -plugin option Alex Bennée
2019-10-17 13:16 ` [PATCH v6 41/54] linux-user: " Alex Bennée
2019-10-17 13:16 ` [PATCH v6 42/54] tests/plugin: add sample plugins Alex Bennée
2019-10-17 13:16 ` [PATCH v6 43/54] tests/tcg/Makefile.target: fix path to config-host.mak Alex Bennée
2019-10-17 13:16 ` [PATCH v6 44/54] tests/tcg: set QEMU_OPTS for all cris runs Alex Bennée
2019-10-17 13:16 ` [PATCH v6 45/54] tests/tcg: move "virtual" tests to EXTRA_TESTS Alex Bennée
2019-10-17 13:16 ` [PATCH v6 46/54] tests/tcg: drop test-i386-fprem from TESTS when not SLOW Alex Bennée
2019-10-17 13:16 ` [PATCH v6 47/54] tests/tcg: enable plugin testing Alex Bennée
2019-10-17 13:16 ` [PATCH v6 48/54] tests/plugin: add a hotblocks plugin Alex Bennée
2019-10-17 13:16 ` [PATCH v6 49/54] tests/plugin: add instruction execution breakdown Alex Bennée
2019-10-17 13:16 ` [PATCH v6 50/54] tests/plugin: add hotpages to analyse memory access patterns Alex Bennée
2019-10-17 13:16 ` [PATCH v6 51/54] accel/stubs: reduce headers from tcg-stub Alex Bennée
2019-10-17 13:16 ` [PATCH v6 52/54] include/exec: wrap cpu_ldst.h in CONFIG_TCG Alex Bennée
2019-10-17 13:16 ` [PATCH v6 53/54] .travis.yml: add --enable-plugins tests Alex Bennée
2019-10-17 13:16 ` [PATCH v6 54/54] scripts/checkpatch.pl: don't complain about (foo, /* empty */) Alex Bennée
2019-10-22 14:12 ` Aaron Lindsay OS
2019-10-17 19:25 ` [PATCH for 4.2 v6 00/54] Support for TCG plugins no-reply
2019-10-18 7:07 ` no-reply
2019-10-18 17:43 ` no-reply
2019-10-22 11:37 ` Alex Bennée
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20191017131615.19660-15-alex.bennee@linaro.org \
--to=alex.bennee@linaro.org \
--cc=aaron@os.amperecomputing.com \
--cc=cota@braap.org \
--cc=pbonzini@redhat.com \
--cc=peter.puhov@futurewei.com \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=riku.voipio@iki.fi \
--cc=robert.foley@futurewei.com \
--cc=rth@twiddle.net \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).