From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [PATCH v7 17/20] target/arm: Rebuild hflags at MSR writes
Date: Thu, 17 Oct 2019 11:51:07 -0700 [thread overview]
Message-ID: <20191017185110.539-18-richard.henderson@linaro.org> (raw)
In-Reply-To: <20191017185110.539-1-richard.henderson@linaro.org>
Continue setting, but not relying upon, env->hflags.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 13 +++++++++++--
target/arm/translate.c | 28 +++++++++++++++++++++++-----
2 files changed, 34 insertions(+), 7 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2d6cd09634..d4bebbe629 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1789,8 +1789,17 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
/* I/O operations must end the TB here (whether read or write) */
s->base.is_jmp = DISAS_UPDATE;
- } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
- /* We default to ending the TB on a coprocessor register write,
+ }
+ if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
+ /*
+ * A write to any coprocessor regiser that ends a TB
+ * must rebuild the hflags for the next TB.
+ */
+ TCGv_i32 tcg_el = tcg_const_i32(s->current_el);
+ gen_helper_rebuild_hflags_a64(cpu_env, tcg_el);
+ tcg_temp_free_i32(tcg_el);
+ /*
+ * We default to ending the TB on a coprocessor register write,
* but allow this to be suppressed by the register definition
* (usually only necessary to work around guest bugs).
*/
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 698c594e8c..cb47cd9744 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -6890,6 +6890,8 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
ri = get_arm_cp_reginfo(s->cp_regs,
ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2));
if (ri) {
+ bool need_exit_tb;
+
/* Check access permissions */
if (!cp_access_ok(s->current_el, ri, isread)) {
return 1;
@@ -7068,14 +7070,30 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
}
}
- if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
- /* I/O operations must end the TB here (whether read or write) */
- gen_lookup_tb(s);
- } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
- /* We default to ending the TB on a coprocessor register write,
+ /* I/O operations must end the TB here (whether read or write) */
+ need_exit_tb = ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) &&
+ (ri->type & ARM_CP_IO));
+
+ if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
+ /*
+ * A write to any coprocessor regiser that ends a TB
+ * must rebuild the hflags for the next TB.
+ */
+ TCGv_i32 tcg_el = tcg_const_i32(s->current_el);
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
+ gen_helper_rebuild_hflags_m32(cpu_env, tcg_el);
+ } else {
+ gen_helper_rebuild_hflags_a32(cpu_env, tcg_el);
+ }
+ tcg_temp_free_i32(tcg_el);
+ /*
+ * We default to ending the TB on a coprocessor register write,
* but allow this to be suppressed by the register definition
* (usually only necessary to work around guest bugs).
*/
+ need_exit_tb = true;
+ }
+ if (need_exit_tb) {
gen_lookup_tb(s);
}
--
2.17.1
next prev parent reply other threads:[~2019-10-17 18:55 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-17 18:50 [PATCH v7 00/20] target/arm: Reduce overhead of cpu_get_tb_cpu_state Richard Henderson
2019-10-17 18:50 ` [PATCH v7 01/20] target/arm: Split out rebuild_hflags_common Richard Henderson
2019-10-17 18:50 ` [PATCH v7 02/20] target/arm: Split out rebuild_hflags_a64 Richard Henderson
2019-10-17 18:50 ` [PATCH v7 03/20] target/arm: Split out rebuild_hflags_common_32 Richard Henderson
2019-10-17 18:50 ` [PATCH v7 04/20] target/arm: Split arm_cpu_data_is_big_endian Richard Henderson
2019-10-17 18:50 ` [PATCH v7 05/20] target/arm: Split out rebuild_hflags_m32 Richard Henderson
2019-10-17 18:50 ` [PATCH v7 06/20] target/arm: Reduce tests vs M-profile in cpu_get_tb_cpu_state Richard Henderson
2019-10-17 18:50 ` [PATCH v7 07/20] target/arm: Split out rebuild_hflags_a32 Richard Henderson
2019-10-17 18:50 ` [PATCH v7 08/20] target/arm: Split out rebuild_hflags_aprofile Richard Henderson
2019-10-17 18:50 ` [PATCH v7 09/20] target/arm: Hoist XSCALE_CPAR, VECLEN, VECSTRIDE in cpu_get_tb_cpu_state Richard Henderson
2019-10-17 18:51 ` [PATCH v7 10/20] target/arm: Simplify set of PSTATE_SS " Richard Henderson
2019-10-17 18:51 ` [PATCH v7 11/20] target/arm: Hoist computation of TBFLAG_A32.VFPEN Richard Henderson
2019-10-17 18:51 ` [PATCH v7 12/20] target/arm: Add arm_rebuild_hflags Richard Henderson
2019-10-17 18:51 ` [PATCH v7 13/20] target/arm: Split out arm_mmu_idx_el Richard Henderson
2019-10-17 18:51 ` [PATCH v7 14/20] target/arm: Hoist store to cs_base in cpu_get_tb_cpu_state Richard Henderson
2019-10-17 18:51 ` [PATCH v7 15/20] target/arm: Add HELPER(rebuild_hflags_{a32, a64, m32}) Richard Henderson
2019-10-17 18:51 ` [PATCH v7 16/20] target/arm: Rebuild hflags at EL changes Richard Henderson
2019-10-17 18:51 ` Richard Henderson [this message]
2019-10-18 12:32 ` [PATCH v7 17/20] target/arm: Rebuild hflags at MSR writes Peter Maydell
2019-10-18 14:30 ` Richard Henderson
2019-10-18 14:49 ` Peter Maydell
2019-10-17 18:51 ` [PATCH v7 18/20] target/arm: Rebuild hflags at CPSR writes Richard Henderson
2019-10-17 18:51 ` [PATCH v7 19/20] target/arm: Rebuild hflags for M-profile Richard Henderson
2019-10-18 12:25 ` Peter Maydell
2019-10-18 14:31 ` Richard Henderson
2019-10-18 14:52 ` Peter Maydell
2019-10-18 14:55 ` Peter Maydell
2019-10-17 18:51 ` [PATCH v7 20/20] target/arm: Rely on hflags correct in cpu_get_tb_cpu_state Richard Henderson
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