From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [PATCH v7 06/20] target/arm: Reduce tests vs M-profile in cpu_get_tb_cpu_state
Date: Thu, 17 Oct 2019 11:50:56 -0700 [thread overview]
Message-ID: <20191017185110.539-7-richard.henderson@linaro.org> (raw)
In-Reply-To: <20191017185110.539-1-richard.henderson@linaro.org>
Hoist the computation of some TBFLAG_A32 bits that only apply to
M-profile under a single test for ARM_FEATURE_M.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 49 +++++++++++++++++++++------------------------
1 file changed, 23 insertions(+), 26 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d4303420da..296a4b2232 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11194,6 +11194,29 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
if (arm_feature(env, ARM_FEATURE_M)) {
flags = rebuild_hflags_m32(env, fp_el, mmu_idx);
+
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
+ FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S)
+ != env->v7m.secure) {
+ flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1);
+ }
+
+ if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) &&
+ (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) ||
+ (env->v7m.secure &&
+ !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) {
+ /*
+ * ASPEN is set, but FPCA/SFPA indicate that there is no
+ * active FP context; we must create a new FP context before
+ * executing any FP insn.
+ */
+ flags = FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1);
+ }
+
+ bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK;
+ if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) {
+ flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1);
+ }
} else {
flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0);
}
@@ -11233,32 +11256,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
}
}
- if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
- FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) != env->v7m.secure) {
- flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1);
- }
-
- if (arm_feature(env, ARM_FEATURE_M) &&
- (env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) &&
- (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) ||
- (env->v7m.secure &&
- !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) {
- /*
- * ASPEN is set, but FPCA/SFPA indicate that there is no active
- * FP context; we must create a new FP context before executing
- * any FP insn.
- */
- flags = FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1);
- }
-
- if (arm_feature(env, ARM_FEATURE_M)) {
- bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK;
-
- if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) {
- flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1);
- }
- }
-
if (!arm_feature(env, ARM_FEATURE_M)) {
int target_el = arm_debug_target_el(env);
--
2.17.1
next prev parent reply other threads:[~2019-10-17 19:00 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-17 18:50 [PATCH v7 00/20] target/arm: Reduce overhead of cpu_get_tb_cpu_state Richard Henderson
2019-10-17 18:50 ` [PATCH v7 01/20] target/arm: Split out rebuild_hflags_common Richard Henderson
2019-10-17 18:50 ` [PATCH v7 02/20] target/arm: Split out rebuild_hflags_a64 Richard Henderson
2019-10-17 18:50 ` [PATCH v7 03/20] target/arm: Split out rebuild_hflags_common_32 Richard Henderson
2019-10-17 18:50 ` [PATCH v7 04/20] target/arm: Split arm_cpu_data_is_big_endian Richard Henderson
2019-10-17 18:50 ` [PATCH v7 05/20] target/arm: Split out rebuild_hflags_m32 Richard Henderson
2019-10-17 18:50 ` Richard Henderson [this message]
2019-10-17 18:50 ` [PATCH v7 07/20] target/arm: Split out rebuild_hflags_a32 Richard Henderson
2019-10-17 18:50 ` [PATCH v7 08/20] target/arm: Split out rebuild_hflags_aprofile Richard Henderson
2019-10-17 18:50 ` [PATCH v7 09/20] target/arm: Hoist XSCALE_CPAR, VECLEN, VECSTRIDE in cpu_get_tb_cpu_state Richard Henderson
2019-10-17 18:51 ` [PATCH v7 10/20] target/arm: Simplify set of PSTATE_SS " Richard Henderson
2019-10-17 18:51 ` [PATCH v7 11/20] target/arm: Hoist computation of TBFLAG_A32.VFPEN Richard Henderson
2019-10-17 18:51 ` [PATCH v7 12/20] target/arm: Add arm_rebuild_hflags Richard Henderson
2019-10-17 18:51 ` [PATCH v7 13/20] target/arm: Split out arm_mmu_idx_el Richard Henderson
2019-10-17 18:51 ` [PATCH v7 14/20] target/arm: Hoist store to cs_base in cpu_get_tb_cpu_state Richard Henderson
2019-10-17 18:51 ` [PATCH v7 15/20] target/arm: Add HELPER(rebuild_hflags_{a32, a64, m32}) Richard Henderson
2019-10-17 18:51 ` [PATCH v7 16/20] target/arm: Rebuild hflags at EL changes Richard Henderson
2019-10-17 18:51 ` [PATCH v7 17/20] target/arm: Rebuild hflags at MSR writes Richard Henderson
2019-10-18 12:32 ` Peter Maydell
2019-10-18 14:30 ` Richard Henderson
2019-10-18 14:49 ` Peter Maydell
2019-10-17 18:51 ` [PATCH v7 18/20] target/arm: Rebuild hflags at CPSR writes Richard Henderson
2019-10-17 18:51 ` [PATCH v7 19/20] target/arm: Rebuild hflags for M-profile Richard Henderson
2019-10-18 12:25 ` Peter Maydell
2019-10-18 14:31 ` Richard Henderson
2019-10-18 14:52 ` Peter Maydell
2019-10-18 14:55 ` Peter Maydell
2019-10-17 18:51 ` [PATCH v7 20/20] target/arm: Rely on hflags correct in cpu_get_tb_cpu_state Richard Henderson
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