From: "Cédric Le Goater" <clg@kaod.org>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: "Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Cédric Le Goater" <clg@kaod.org>,
qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
"Greg Kurz" <groug@kaod.org>
Subject: [PATCH v5 3/7] ppc/pnv: Introduce a PnvCore reset handler
Date: Tue, 22 Oct 2019 18:38:08 +0200 [thread overview]
Message-ID: <20191022163812.330-4-clg@kaod.org> (raw)
In-Reply-To: <20191022163812.330-1-clg@kaod.org>
in which individual CPUs are reset. It will ease the introduction of
future change reseting the interrupt presenter from the CPU reset
handler.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
hw/ppc/pnv_core.c | 19 +++++++++++++++----
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index b1a7489e7abf..9f981a4940e6 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -40,9 +40,8 @@ static const char *pnv_core_cpu_typename(PnvCore *pc)
return cpu_type;
}
-static void pnv_cpu_reset(void *opaque)
+static void pnv_core_cpu_reset(PowerPCCPU *cpu)
{
- PowerPCCPU *cpu = opaque;
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
@@ -192,8 +191,17 @@ static void pnv_realize_vcpu(PowerPCCPU *cpu, PnvChip *chip, Error **errp)
/* Set time-base frequency to 512 MHz */
cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
+}
+
+static void pnv_core_reset(void *dev)
+{
+ CPUCore *cc = CPU_CORE(dev);
+ PnvCore *pc = PNV_CORE(dev);
+ int i;
- qemu_register_reset(pnv_cpu_reset, cpu);
+ for (i = 0; i < cc->nr_threads; i++) {
+ pnv_core_cpu_reset(pc->threads[i]);
+ }
}
static void pnv_core_realize(DeviceState *dev, Error **errp)
@@ -244,6 +252,8 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops,
pc, name, PNV_XSCOM_EX_SIZE);
+
+ qemu_register_reset(pnv_core_reset, pc);
return;
err:
@@ -259,7 +269,6 @@ static void pnv_unrealize_vcpu(PowerPCCPU *cpu)
{
PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
- qemu_unregister_reset(pnv_cpu_reset, cpu);
object_unparent(OBJECT(pnv_cpu_state(cpu)->intc));
cpu_remove_sync(CPU(cpu));
cpu->machine_data = NULL;
@@ -273,6 +282,8 @@ static void pnv_core_unrealize(DeviceState *dev, Error **errp)
CPUCore *cc = CPU_CORE(dev);
int i;
+ qemu_unregister_reset(pnv_core_reset, pc);
+
for (i = 0; i < cc->nr_threads; i++) {
pnv_unrealize_vcpu(pc->threads[i]);
}
--
2.21.0
next prev parent reply other threads:[~2019-10-22 16:58 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-22 16:38 [PATCH v5 0/7] ppc: reset the interrupt presenter from the CPU reset handler Cédric Le Goater
2019-10-22 16:38 ` [PATCH v5 1/7] spapr: move CPU reset after presenter creation Cédric Le Goater
2019-10-22 16:38 ` [PATCH v5 2/7] spapr_cpu_core: Implement DeviceClass::reset Cédric Le Goater
2019-10-22 16:38 ` Cédric Le Goater [this message]
2019-10-23 11:18 ` [PATCH v5 3/7] ppc/pnv: Introduce a PnvCore reset handler Philippe Mathieu-Daudé
2019-10-24 2:33 ` David Gibson
2019-10-22 16:38 ` [PATCH v5 4/7] ppc/pnv: Add a PnvChip pointer to PnvCore Cédric Le Goater
2019-10-23 11:19 ` Philippe Mathieu-Daudé
2019-10-24 2:38 ` David Gibson
2019-10-24 9:57 ` Cédric Le Goater
2019-10-24 16:48 ` Greg Kurz
2019-10-27 16:54 ` David Gibson
2019-10-27 16:52 ` David Gibson
2019-10-24 17:30 ` Greg Kurz
2019-10-27 16:54 ` David Gibson
2019-10-22 16:38 ` [PATCH v5 5/7] ppc: Reset the interrupt presenter from the CPU reset handler Cédric Le Goater
2019-10-22 20:26 ` Greg Kurz
2019-10-23 11:25 ` Philippe Mathieu-Daudé
2019-10-24 2:40 ` David Gibson
2019-10-22 16:38 ` [PATCH v5 6/7] ppc/pnv: Fix naming of routines realizing the CPUs Cédric Le Goater
2019-10-23 11:26 ` Philippe Mathieu-Daudé
2019-10-22 16:38 ` [PATCH v5 7/7] spapr/xive: Set the OS CAM line at reset Cédric Le Goater
2019-10-24 2:41 ` David Gibson
2019-10-24 2:35 ` [PATCH v5 0/7] ppc: reset the interrupt presenter from the CPU reset handler David Gibson
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