From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [PATCH v9 17/24] target/arm: Rebuild hflags at MSR writes
Date: Wed, 23 Oct 2019 11:00:50 -0400 [thread overview]
Message-ID: <20191023150057.25731-18-richard.henderson@linaro.org> (raw)
In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org>
Continue setting, but not relying upon, env->hflags.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 13 +++++++++++--
target/arm/translate.c | 28 +++++++++++++++++++++++-----
2 files changed, 34 insertions(+), 7 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2d6cd09634..d4bebbe629 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1789,8 +1789,17 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
/* I/O operations must end the TB here (whether read or write) */
s->base.is_jmp = DISAS_UPDATE;
- } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
- /* We default to ending the TB on a coprocessor register write,
+ }
+ if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
+ /*
+ * A write to any coprocessor regiser that ends a TB
+ * must rebuild the hflags for the next TB.
+ */
+ TCGv_i32 tcg_el = tcg_const_i32(s->current_el);
+ gen_helper_rebuild_hflags_a64(cpu_env, tcg_el);
+ tcg_temp_free_i32(tcg_el);
+ /*
+ * We default to ending the TB on a coprocessor register write,
* but allow this to be suppressed by the register definition
* (usually only necessary to work around guest bugs).
*/
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 96340520ee..46a0bf51c9 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -6890,6 +6890,8 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
ri = get_arm_cp_reginfo(s->cp_regs,
ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2));
if (ri) {
+ bool need_exit_tb;
+
/* Check access permissions */
if (!cp_access_ok(s->current_el, ri, isread)) {
return 1;
@@ -7068,14 +7070,30 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
}
}
- if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
- /* I/O operations must end the TB here (whether read or write) */
- gen_lookup_tb(s);
- } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
- /* We default to ending the TB on a coprocessor register write,
+ /* I/O operations must end the TB here (whether read or write) */
+ need_exit_tb = ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) &&
+ (ri->type & ARM_CP_IO));
+
+ if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
+ /*
+ * A write to any coprocessor regiser that ends a TB
+ * must rebuild the hflags for the next TB.
+ */
+ TCGv_i32 tcg_el = tcg_const_i32(s->current_el);
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
+ gen_helper_rebuild_hflags_m32(cpu_env, tcg_el);
+ } else {
+ gen_helper_rebuild_hflags_a32(cpu_env, tcg_el);
+ }
+ tcg_temp_free_i32(tcg_el);
+ /*
+ * We default to ending the TB on a coprocessor register write,
* but allow this to be suppressed by the register definition
* (usually only necessary to work around guest bugs).
*/
+ need_exit_tb = true;
+ }
+ if (need_exit_tb) {
gen_lookup_tb(s);
}
--
2.17.1
next prev parent reply other threads:[~2019-10-23 15:28 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-23 15:00 [PATCH v9 00/24] target/arm: Reduce overhead of cpu_get_tb_cpu_state Richard Henderson
2019-10-23 15:00 ` [PATCH v9 01/24] target/arm: Split out rebuild_hflags_common Richard Henderson
2019-10-23 15:00 ` [PATCH v9 02/24] target/arm: Split out rebuild_hflags_a64 Richard Henderson
2019-10-23 15:00 ` [PATCH v9 03/24] target/arm: Split out rebuild_hflags_common_32 Richard Henderson
2019-10-23 15:00 ` [PATCH v9 04/24] target/arm: Split arm_cpu_data_is_big_endian Richard Henderson
2019-10-23 15:00 ` [PATCH v9 05/24] target/arm: Split out rebuild_hflags_m32 Richard Henderson
2019-10-23 15:00 ` [PATCH v9 06/24] target/arm: Reduce tests vs M-profile in cpu_get_tb_cpu_state Richard Henderson
2019-10-23 15:00 ` [PATCH v9 07/24] target/arm: Split out rebuild_hflags_a32 Richard Henderson
2019-10-23 15:00 ` [PATCH v9 08/24] target/arm: Split out rebuild_hflags_aprofile Richard Henderson
2019-10-23 15:00 ` [PATCH v9 09/24] target/arm: Hoist XSCALE_CPAR, VECLEN, VECSTRIDE in cpu_get_tb_cpu_state Richard Henderson
2019-10-23 15:00 ` [PATCH v9 10/24] target/arm: Simplify set of PSTATE_SS " Richard Henderson
2019-10-23 15:00 ` [PATCH v9 11/24] target/arm: Hoist computation of TBFLAG_A32.VFPEN Richard Henderson
2019-10-23 15:00 ` [PATCH v9 12/24] target/arm: Add arm_rebuild_hflags Richard Henderson
2019-10-23 15:00 ` [PATCH v9 13/24] target/arm: Split out arm_mmu_idx_el Richard Henderson
2019-10-23 15:00 ` [PATCH v9 14/24] target/arm: Hoist store to cs_base in cpu_get_tb_cpu_state Richard Henderson
2019-10-23 15:00 ` [PATCH v9 15/24] target/arm: Add HELPER(rebuild_hflags_{a32, a64, m32}) Richard Henderson
2019-10-23 15:00 ` [PATCH v9 16/24] target/arm: Rebuild hflags at EL changes Richard Henderson
2019-10-23 15:00 ` Richard Henderson [this message]
2019-10-23 15:00 ` [PATCH v9 18/24] target/arm: Rebuild hflags at CPSR writes Richard Henderson
2019-10-23 15:00 ` [PATCH v9 19/24] target/arm: Rebuild hflags at Xscale SCTLR writes Richard Henderson
2019-10-23 15:00 ` [PATCH v9 20/24] target/arm: Rebuild hflags for M-profile Richard Henderson
2019-10-23 15:00 ` [PATCH v9 21/24] target/arm: Rebuild hflags for M-profile NVIC Richard Henderson
2019-10-23 15:00 ` [PATCH v9 22/24] linux-user/aarch64: Rebuild hflags for TARGET_WORDS_BIGENDIAN Richard Henderson
2019-10-23 15:00 ` [PATCH v9 23/24] linux-user/arm: " Richard Henderson
2019-10-23 15:00 ` [PATCH v9 24/24] target/arm: Rely on hflags correct in cpu_get_tb_cpu_state Richard Henderson
2019-10-24 11:41 ` [PATCH v9 00/24] target/arm: Reduce overhead of cpu_get_tb_cpu_state Peter Maydell
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