From: hiroyuki.obinata@gmail.com
To: qemu-devel@nongnu.org
Cc: "open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
"hiroyuki.obinata" <hiroyuki.obinata@gmail.com>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmer@sifive.com>,
Alistair Francis <Alistair.Francis@wdc.com>
Subject: [PATCH] remove unnecessary ifdef TARGET_RISCV64
Date: Wed, 30 Oct 2019 09:23:18 +0900 [thread overview]
Message-ID: <20191030002318.399-1-hiroyuki.obinata@gmail.com> (raw)
From: "hiroyuki.obinata" <hiroyuki.obinata@gmail.com>
Signed-off-by: Hiroyuki Obinata <hiroyuki.obinata@gmail.com>
---
target/riscv/translate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index adeddb85f6..5c4dd21a98 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -64,12 +64,10 @@ static const int tcg_memop_lookup[8] = {
[0] = MO_SB,
[1] = MO_TESW,
[2] = MO_TESL,
+ [3] = MO_TEQ,
[4] = MO_UB,
[5] = MO_TEUW,
-#ifdef TARGET_RISCV64
- [3] = MO_TEQ,
[6] = MO_TEUL,
-#endif
};
#endif
--
2.17.1
next reply other threads:[~2019-10-30 0:58 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-30 0:23 hiroyuki.obinata [this message]
2019-11-01 16:58 ` [PATCH] remove unnecessary ifdef TARGET_RISCV64 Palmer Dabbelt
2019-11-02 1:16 ` Obinata Hiroyuki
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