[PULL] RISC-V Fixes for 4.2-rc2

[Palmer Dabbelt <palmer@dabbelt.com>]

The following changes since commit aa464db69b40b4b695be31085e6d2f1e90956c89:

  Update version for v4.2.0-rc1 release (2019-11-12 18:40:02 +0000)

are available in the Git repository at:

  git@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-4.2-rc2

for you to fetch changes up to 6911fde41006b2afe3510755c4cff259ca56c1d9:

  riscv/virt: Increase flash size (2019-11-14 09:53:28 -0800)

----------------------------------------------------------------
RISC-V Fixes for 4.2-rc2

This contains a handful of patches that I'd like to target for 4.2:

* OpenSBI upgrade to 0.5
* Increase in the flash size of the virt board.
* A non-functional cleanup.
* A cleanup to our MIP handling that avoids atomics.

This passes "make check" and boots OpenEmbedded for me.

----------------------------------------------------------------
Alistair Francis (3):
      target/riscv: Remove atomic accesses to MIP CSR
      opensbi: Upgrade from v0.4 to v0.5
      riscv/virt: Increase flash size

hiroyuki.obinata (1):
      remove unnecessary ifdef TARGET_RISCV64

 hw/riscv/virt.c                              |   2 +-
 pc-bios/opensbi-riscv32-virt-fw_jump.bin     | Bin 36888 -> 40984 bytes
 pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin 45064 -> 49160 bytes
 pc-bios/opensbi-riscv64-virt-fw_jump.bin     | Bin 40968 -> 45064 bytes
 roms/opensbi                                 |   2 +-
 target/riscv/cpu.c                           |   5 ++-
 target/riscv/cpu.h                           |   9 -----
 target/riscv/cpu_helper.c                    |  48 ++++++++++-----------------
 target/riscv/csr.c                           |   2 +-
 target/riscv/translate.c                     |   4 +--
 10 files changed, 24 insertions(+), 48 deletions(-)