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From: Palmer Dabbelt <palmer@dabbelt.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Palmer Dabbelt <palmer@sifive.com>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	"hiroyuki.obinata" <hiroyuki.obinata@gmail.com>
Subject: [PULL 1/4] remove unnecessary ifdef TARGET_RISCV64
Date: Thu, 14 Nov 2019 20:41:01 -0800	[thread overview]
Message-ID: <20191115044104.4197-2-palmer@dabbelt.com> (raw)
In-Reply-To: <20191115044104.4197-1-palmer@dabbelt.com>

From: "hiroyuki.obinata" <hiroyuki.obinata@gmail.com>

Signed-off-by: Hiroyuki Obinata <hiroyuki.obinata@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 target/riscv/translate.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b26533d4fd78..ab6a891dc381 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -64,12 +64,10 @@ static const int tcg_memop_lookup[8] = {
     [0] = MO_SB,
     [1] = MO_TESW,
     [2] = MO_TESL,
+    [3] = MO_TEQ,
     [4] = MO_UB,
     [5] = MO_TEUW,
-#ifdef TARGET_RISCV64
-    [3] = MO_TEQ,
     [6] = MO_TEUL,
-#endif
 };
 #endif
 
-- 
2.21.0



  reply	other threads:[~2019-11-15  4:42 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-15  4:41 [PULL] RISC-V Fixes for 4.2-rc2 Palmer Dabbelt
2019-11-15  4:41 ` Palmer Dabbelt [this message]
2019-11-15  4:41 ` [PULL 2/4] target/riscv: Remove atomic accesses to MIP CSR Palmer Dabbelt
2019-11-15  4:41 ` [PULL 3/4] opensbi: Upgrade from v0.4 to v0.5 Palmer Dabbelt
2019-11-15  4:41 ` [PULL 4/4] riscv/virt: Increase flash size Palmer Dabbelt
2019-11-15 12:34 ` [PULL] RISC-V Fixes for 4.2-rc2 Peter Maydell

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