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From: Palmer Dabbelt <palmer@dabbelt.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Alistair Francis <alistair.francis@wdc.com>,
	Palmer Dabbelt <palmer@sifive.com>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Subject: [PULL 4/4] riscv/virt: Increase flash size
Date: Thu, 14 Nov 2019 20:41:04 -0800	[thread overview]
Message-ID: <20191115044104.4197-5-palmer@dabbelt.com> (raw)
In-Reply-To: <20191115044104.4197-1-palmer@dabbelt.com>

From: Alistair Francis <alistair.francis@wdc.com>

Coreboot developers have requested that they have at least 32MB of flash
to load binaries. We currently have 32MB of flash, but it is split in
two to allow loading two flash binaries. Let's increase the flash size
from 32MB to 64MB to ensure we have a single region that is 32MB.

No QEMU release has include flash in the RISC-V virt machine, so this
isn't a breaking change.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 hw/riscv/virt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index cc8f311e6bbb..23f340df193e 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -62,7 +62,7 @@ static const struct MemmapEntry {
     [VIRT_PLIC] =        {  0xc000000,     0x4000000 },
     [VIRT_UART0] =       { 0x10000000,         0x100 },
     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
-    [VIRT_FLASH] =       { 0x20000000,     0x2000000 },
+    [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
     [VIRT_DRAM] =        { 0x80000000,           0x0 },
     [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
     [VIRT_PCIE_PIO] =    { 0x03000000,    0x00010000 },
-- 
2.21.0



  parent reply	other threads:[~2019-11-15  4:44 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-15  4:41 [PULL] RISC-V Fixes for 4.2-rc2 Palmer Dabbelt
2019-11-15  4:41 ` [PULL 1/4] remove unnecessary ifdef TARGET_RISCV64 Palmer Dabbelt
2019-11-15  4:41 ` [PULL 2/4] target/riscv: Remove atomic accesses to MIP CSR Palmer Dabbelt
2019-11-15  4:41 ` [PULL 3/4] opensbi: Upgrade from v0.4 to v0.5 Palmer Dabbelt
2019-11-15  4:41 ` Palmer Dabbelt [this message]
2019-11-15 12:34 ` [PULL] RISC-V Fixes for 4.2-rc2 Peter Maydell

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