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Iglesias" To: Sai Pavan Boddu Subject: Re: [PATCH v6] ssi: xilinx_spips: Skip spi bus update for a few register writes Message-ID: <20191115154925.GD2859@toto> References: <1573830705-14579-1-git-send-email-sai.pavan.boddu@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1573830705-14579-1-git-send-email-sai.pavan.boddu@xilinx.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(7916004)(136003)(346002)(396003)(376002)(39860400002)(189003)(199004)(54906003)(16586007)(33656002)(305945005)(229853002)(316002)(58126008)(1076003)(14444005)(4326008)(50466002)(70206006)(70586007)(76176011)(6246003)(356004)(6862004)(36386004)(2906002)(106002)(23726003)(8676002)(486006)(57986006)(126002)(476003)(15650500001)(33716001)(186003)(5660300002)(76506006)(336012)(11346002)(426003)(446003)(9786002)(9686003)(81156014)(26005)(81166006)(8936002)(478600001)(47776003)(6636002); DIR:OUT; SFP:1101; SCL:1; SRVR:DM6PR02MB3930; H:xsj-pvapsmtpgw01; FPR:; SPF:Pass; LANG:en; PTR:unknown-60-83.xilinx.com; MX:1; A:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a16b955f-d200-4809-7de0-08d769e36ac2 X-MS-TrafficTypeDiagnostic: DM6PR02MB3930: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:170; X-Forefront-PRVS: 02229A4115 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TXMC9Rgs9BjavIoUAPzGD+K9DmM50QRBEOAsqOqNNa+caHpaqiyiR5WqXfGiZv2dR80npFiGdTOepWPbkGhEC7pNk8HQUVMDSenAi1phnMqtkvW1nDLEGh+VayPTyLKpxJgdo/COO9Rszf30o8C1QpDhBxdNtdESExVE2vpMTTYvT8WxOAJvomCT9cy3N4nM9No4KM1OIpfpDb+sVokqo+YjhWI0Cs7rJglCZIDPbFT3J2ShfZg9ZIGQ8riX4ZiLXJqcPMjcei26SSxH3jjJRCmmoOIz068oo+8/8HSz4ygcwbB2Rpq+xlxy5WeNTIeawpO8JMxxtImaUyzOwtwzDBLL4eZBE1We/gsbfaV2mnFzFRZnOtX2DOBDNi5k7IBFRR0tTrlyQFU88Mb5YeR3WcYgxj9Wdb1Pf6BcO1Y2hm87P5kNnMBPIV4uG6w+n2Hr X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2019 15:49:36.4106 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a16b955f-d200-4809-7de0-08d769e36ac2 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB3930 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.73.66 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Francisco Iglesias , Alistair Francis , qemu-devel@nongnu.org, peter.maydell@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, Nov 15, 2019 at 08:41:45PM +0530, Sai Pavan Boddu wrote: > A few configuration register writes need not update the spi bus state, so just > return after the register write. > > Signed-off-by: Sai Pavan Boddu > Reviewed-by: Alistair Francis > Reviewed-by: Francisco Iglesias > Tested-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias > --- > > Changes for V2: > Just skip update of spips cs and fifos > Update commit message accordingly > Changes for V4: > Avoid checking for zynqmp qspi > Skip spi bus update for few of the registers Changes for V4: > Move the register list to existing switch case above. > Changes for V5: > Fixed Commit message. > Changes for V6: > Fixed commit message. Added Review tags. > > Note: Resending this as it got filtered for first two attempts. > > > hw/ssi/xilinx_spips.c | 22 ++++++++++++++++++---- > 1 file changed, 18 insertions(+), 4 deletions(-) > > diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c > index a309c71..0d6c2e1 100644 > --- a/hw/ssi/xilinx_spips.c > +++ b/hw/ssi/xilinx_spips.c > @@ -109,6 +109,7 @@ > #define R_GPIO (0x30 / 4) > #define R_LPBK_DLY_ADJ (0x38 / 4) > #define R_LPBK_DLY_ADJ_RESET (0x33) > +#define R_IOU_TAPDLY_BYPASS (0x3C / 4) > #define R_TXD1 (0x80 / 4) > #define R_TXD2 (0x84 / 4) > #define R_TXD3 (0x88 / 4) > @@ -139,6 +140,8 @@ > #define R_LQSPI_STS (0xA4 / 4) > #define LQSPI_STS_WR_RECVD (1 << 1) > > +#define R_DUMMY_CYCLE_EN (0xC8 / 4) > +#define R_ECO (0xF8 / 4) > #define R_MOD_ID (0xFC / 4) > > #define R_GQSPI_SELECT (0x144 / 4) > @@ -970,6 +973,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, > { > int mask = ~0; > XilinxSPIPS *s = opaque; > + bool try_flush = true; > > DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); > addr >>= 2; > @@ -1019,13 +1023,23 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, > tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, > s->regs[R_CONFIG] & R_CONFIG_ENDIAN); > goto no_reg_update; > + /* Skip SPI bus update for below registers writes */ > + case R_GPIO: > + case R_LPBK_DLY_ADJ: > + case R_IOU_TAPDLY_BYPASS: > + case R_DUMMY_CYCLE_EN: > + case R_ECO: > + try_flush = false; > + break; > } > s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); > no_reg_update: > - xilinx_spips_update_cs_lines(s); > - xilinx_spips_check_flush(s); > - xilinx_spips_update_cs_lines(s); > - xilinx_spips_update_ixr(s); > + if (try_flush) { > + xilinx_spips_update_cs_lines(s); > + xilinx_spips_check_flush(s); > + xilinx_spips_update_cs_lines(s); > + xilinx_spips_update_ixr(s); > + } > } > > static const MemoryRegionOps spips_ops = { > -- > 2.7.4 >