From: "Michael S. Tsirkin" <mst@redhat.com>
To: qi1.zhang@intel.com
Cc: ehabkost@redhat.com, qemu-devel@nongnu.org, pbonzini@redhat.com,
yadong.qi@intel.com, rth@twiddle.net
Subject: Re: [PATCH v2 2/2] intel_iommu: TM field should not be in reserved bits
Date: Tue, 19 Nov 2019 06:06:05 -0500 [thread overview]
Message-ID: <20191119060551-mutt-send-email-mst@kernel.org> (raw)
In-Reply-To: <758ae02ef3a36b2790a7e61018bb55379ceeb450.1570503331.git.qi1.zhang@intel.com>
On Tue, Nov 19, 2019 at 08:28:14PM +0800, qi1.zhang@intel.com wrote:
> From: "Zhang, Qi" <qi1.zhang@intel.com>
>
> When dt is supported, TM field should not be Reserved(0).
>
> Refer to VT-d Spec 9.8
>
> Signed-off-by: Zhang, Qi <qi1.zhang@intel.com>
> Signed-off-by: Qi, Yadong <yadong.qi@intel.com>
OK and we want to CC stable on this I guess?
> ---
> hw/i386/intel_iommu.c | 12 ++++++++----
> hw/i386/intel_iommu_internal.h | 17 +++++++++++++----
> 2 files changed, 21 insertions(+), 8 deletions(-)
>
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index a118efaeaf..d62604ece3 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -3549,15 +3549,19 @@ static void vtd_init(IntelIOMMUState *s)
> * Rsvd field masks for spte
> */
> vtd_spte_rsvd[0] = ~0ULL;
> - vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
> + vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits,
> + x86_iommu->dt_supported);
> vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
> vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
> vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
>
> vtd_spte_rsvd_large[0] = ~0ULL;
> - vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
> - vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
> - vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
> + vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits,
> + x86_iommu->dt_supported);
> + vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits,
> + x86_iommu->dt_supported);
> + vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits,
> + x86_iommu->dt_supported);
> vtd_spte_rsvd_large[4] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
>
> if (x86_iommu_ir_supported(x86_iommu)) {
> diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
> index c1235a7063..3a839a8925 100644
> --- a/hw/i386/intel_iommu_internal.h
> +++ b/hw/i386/intel_iommu_internal.h
> @@ -387,7 +387,9 @@ typedef union VTDInvDesc VTDInvDesc;
> #define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8
>
> /* Rsvd field masks for spte */
> -#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \
> +#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \
> + dt_supported ? \
> + (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
> (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
> #define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \
> (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
> @@ -395,11 +397,17 @@ typedef union VTDInvDesc VTDInvDesc;
> (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
> #define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \
> (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
> -#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw) \
> +#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw, dt_supported) \
> + dt_supported ? \
> + (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
> (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
> -#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \
> +#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, dt_supported) \
> + dt_supported ? \
> + (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
> (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
> -#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \
> +#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, dt_supported) \
> + dt_supported ? \
> + (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
> (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
> #define VTD_SPTE_LPAGE_L4_RSVD_MASK(aw) \
> (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
> @@ -506,5 +514,6 @@ typedef struct VTDRootEntry VTDRootEntry;
> #define VTD_SL_W (1ULL << 1)
> #define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw))
> #define VTD_SL_IGN_COM 0xbff0000000000000ULL
> +#define VTD_SL_TM (1ULL << 62)
>
> #endif
> --
> 2.20.1
next prev parent reply other threads:[~2019-11-19 11:08 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-19 12:27 [PATCH v2 0/2] TM field check failed qi1.zhang
2019-11-19 11:05 ` Michael S. Tsirkin
2019-11-19 16:21 ` Peter Xu
2019-11-19 16:39 ` Michael S. Tsirkin
2019-11-19 17:01 ` Peter Xu
2019-11-19 12:27 ` [PATCH 1/2] intel_iommu: split the resevred fields arrays into two ones qi1.zhang
2019-11-19 12:28 ` [PATCH v2 " qi1.zhang
2019-11-19 16:06 ` Peter Xu
2019-11-22 8:10 ` Qi, Yadong
2019-11-19 12:28 ` [PATCH v2 0/2] TM field check failed qi1.zhang
2019-11-19 12:28 ` [PATCH v2 2/2] intel_iommu: TM field should not be in reserved bits qi1.zhang
2019-11-19 11:06 ` Michael S. Tsirkin [this message]
2019-11-19 12:27 ` [PATCH " qi1.zhang
-- strict thread matches above, loose matches on Subject: below --
2019-10-08 1:39 [PATCH 0/2] TM field check failed qi1.zhang
2019-10-08 1:39 ` [PATCH 2/2] intel_iommu: TM field should not be in reserved bits qi1.zhang
2019-10-08 2:34 ` [PATCH v2 " qi1.zhang
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