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[79.176.6.42]) by smtp.gmail.com with ESMTPSA id h3sm12752278qte.62.2019.11.19.03.06.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2019 03:06:10 -0800 (PST) Date: Tue, 19 Nov 2019 06:06:05 -0500 From: "Michael S. Tsirkin" To: qi1.zhang@intel.com Subject: Re: [PATCH v2 2/2] intel_iommu: TM field should not be in reserved bits Message-ID: <20191119060551-mutt-send-email-mst@kernel.org> References: <758ae02ef3a36b2790a7e61018bb55379ceeb450.1570503331.git.qi1.zhang@intel.com> MIME-Version: 1.0 In-Reply-To: <758ae02ef3a36b2790a7e61018bb55379ceeb450.1570503331.git.qi1.zhang@intel.com> X-MC-Unique: pQDWjUj9MQqR1OWYOZ54NQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ehabkost@redhat.com, qemu-devel@nongnu.org, pbonzini@redhat.com, yadong.qi@intel.com, rth@twiddle.net Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Nov 19, 2019 at 08:28:14PM +0800, qi1.zhang@intel.com wrote: > From: "Zhang, Qi" >=20 > When dt is supported, TM field should not be Reserved(0). >=20 > Refer to VT-d Spec 9.8 >=20 > Signed-off-by: Zhang, Qi > Signed-off-by: Qi, Yadong OK and we want to CC stable on this I guess? > --- > hw/i386/intel_iommu.c | 12 ++++++++---- > hw/i386/intel_iommu_internal.h | 17 +++++++++++++---- > 2 files changed, 21 insertions(+), 8 deletions(-) >=20 > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index a118efaeaf..d62604ece3 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -3549,15 +3549,19 @@ static void vtd_init(IntelIOMMUState *s) > * Rsvd field masks for spte > */ > vtd_spte_rsvd[0] =3D ~0ULL; > - vtd_spte_rsvd[1] =3D VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits); > + vtd_spte_rsvd[1] =3D VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits, > + x86_iommu->dt_supporte= d); > vtd_spte_rsvd[2] =3D VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits); > vtd_spte_rsvd[3] =3D VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits); > vtd_spte_rsvd[4] =3D VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits); > =20 > vtd_spte_rsvd_large[0] =3D ~0ULL; > - vtd_spte_rsvd_large[1] =3D VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits); > - vtd_spte_rsvd_large[2] =3D VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits); > - vtd_spte_rsvd_large[3] =3D VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits); > + vtd_spte_rsvd_large[1] =3D VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits, > + x86_iommu->dt_s= upported); > + vtd_spte_rsvd_large[2] =3D VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits, > + x86_iommu->dt_s= upported); > + vtd_spte_rsvd_large[3] =3D VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits, > + x86_iommu->dt_s= upported); > vtd_spte_rsvd_large[4] =3D VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits); > =20 > if (x86_iommu_ir_supported(x86_iommu)) { > diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_interna= l.h > index c1235a7063..3a839a8925 100644 > --- a/hw/i386/intel_iommu_internal.h > +++ b/hw/i386/intel_iommu_internal.h > @@ -387,7 +387,9 @@ typedef union VTDInvDesc VTDInvDesc; > #define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8 > =20 > /* Rsvd field masks for spte */ > -#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \ > +#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \ > + dt_supported ? \ > + (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : = \ > (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > #define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \ > (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > @@ -395,11 +397,17 @@ typedef union VTDInvDesc VTDInvDesc; > (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > #define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \ > (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > -#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw) \ > +#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw, dt_supported) \ > + dt_supported ? \ > + (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : = \ > (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > -#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \ > +#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, dt_supported) \ > + dt_supported ? \ > + (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM))= : \ > (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > -#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \ > +#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, dt_supported) \ > + dt_supported ? \ > + (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM= )) : \ > (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > #define VTD_SPTE_LPAGE_L4_RSVD_MASK(aw) \ > (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > @@ -506,5 +514,6 @@ typedef struct VTDRootEntry VTDRootEntry; > #define VTD_SL_W (1ULL << 1) > #define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MAS= K(aw)) > #define VTD_SL_IGN_COM 0xbff0000000000000ULL > +#define VTD_SL_TM (1ULL << 62) > =20 > #endif > --=20 > 2.20.1