From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 4/7] net/cadence_gem: Set PHY autonegotiation restart status
Date: Tue, 19 Nov 2019 13:31:42 +0000 [thread overview]
Message-ID: <20191119133145.31466-5-peter.maydell@linaro.org> (raw)
In-Reply-To: <20191119133145.31466-1-peter.maydell@linaro.org>
From: Linus Ziegert <linus.ziegert+qemu@holoplot.com>
The Linux kernel PHY driver sets AN_RESTART in the BMCR of the
PHY when autonegotiation is started.
Recently the kernel started to read back the PHY's AN_RESTART
bit and now checks whether the autonegotiation is complete and
the bit was cleared [1]. Otherwise the link status is down.
The emulated PHY needs to clear AN_RESTART immediately to inform
the kernel driver about the completion of autonegotiation phase.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c36757eb9dee
Signed-off-by: Linus Ziegert <linus.ziegert+qemu@holoplot.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20191104181604.21943-1-linus.ziegert+qemu@holoplot.com
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/net/cadence_gem.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 7f9cb5ab955..b8be73dc558 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -271,9 +271,10 @@
#define PHY_REG_EXT_PHYSPCFC_ST 27
#define PHY_REG_CABLE_DIAG 28
-#define PHY_REG_CONTROL_RST 0x8000
-#define PHY_REG_CONTROL_LOOP 0x4000
-#define PHY_REG_CONTROL_ANEG 0x1000
+#define PHY_REG_CONTROL_RST 0x8000
+#define PHY_REG_CONTROL_LOOP 0x4000
+#define PHY_REG_CONTROL_ANEG 0x1000
+#define PHY_REG_CONTROL_ANRESTART 0x0200
#define PHY_REG_STATUS_LINK 0x0004
#define PHY_REG_STATUS_ANEGCMPL 0x0020
@@ -1345,7 +1346,7 @@ static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val)
}
if (val & PHY_REG_CONTROL_ANEG) {
/* Complete autonegotiation immediately */
- val &= ~PHY_REG_CONTROL_ANEG;
+ val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART);
s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL;
}
if (val & PHY_REG_CONTROL_LOOP) {
--
2.20.1
next prev parent reply other threads:[~2019-11-19 13:34 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-19 13:31 [PULL 0/7] target-arm queue Peter Maydell
2019-11-19 13:31 ` [PULL 1/7] pl031: Expose RTCICR as proper WC register Peter Maydell
2019-11-19 13:31 ` [PULL 2/7] target/arm: Merge arm_cpu_vq_map_next_smaller into sole caller Peter Maydell
2019-11-19 13:31 ` [PULL 3/7] ssi: xilinx_spips: Skip spi bus update for a few register writes Peter Maydell
2019-11-19 13:31 ` Peter Maydell [this message]
2019-11-19 13:31 ` [PULL 5/7] target/arm: Do not reject rt == rt2 for strexd Peter Maydell
2019-11-19 13:31 ` [PULL 6/7] target/arm: Relax r13 restriction for ldrex/strex for v8.0 Peter Maydell
2019-11-19 13:31 ` [PULL 7/7] target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY Peter Maydell
2019-11-19 15:55 ` [PULL 0/7] target-arm queue Peter Maydell
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