From: Peter Xu <peterx@redhat.com>
To: "Michael S. Tsirkin" <mst@redhat.com>
Cc: qi1.zhang@intel.com, ehabkost@redhat.com, qemu-devel@nongnu.org,
pbonzini@redhat.com, yadong.qi@intel.com, rth@twiddle.net
Subject: Re: [PATCH v2 0/2] TM field check failed
Date: Tue, 19 Nov 2019 11:21:10 -0500 [thread overview]
Message-ID: <20191119162110.GL9053@xz-x1> (raw)
In-Reply-To: <20191119060259-mutt-send-email-mst@kernel.org>
On Tue, Nov 19, 2019 at 06:05:11AM -0500, Michael S. Tsirkin wrote:
> On Tue, Nov 19, 2019 at 08:28:12PM +0800, qi1.zhang@intel.com wrote:
> > From: "Zhang, Qi" <qi1.zhang@intel.com>
> >
> > spilt the reserved fields arrays and remove TM field from reserved
> > bits
>
> Looks good to me.
> Also Cc Peter Xu.
> Also I wonder - do we need to version this change
> with the machine type? Peter what's your take?
It should be a bugfix to me. With the patchset we check even less
reserved bits, then imho it shouldn't break any existing good users.
So we can probably skip versioning this change.
> Also, Peter, how about we create a MAINTAINERS entry for IOMMUs
> and add everyone involved, this way people will
> remember to CC you?
Sure, I'll be fine with either way.
Thanks,
--
Peter Xu
next prev parent reply other threads:[~2019-11-19 16:32 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-19 12:27 [PATCH v2 0/2] TM field check failed qi1.zhang
2019-11-19 11:05 ` Michael S. Tsirkin
2019-11-19 16:21 ` Peter Xu [this message]
2019-11-19 16:39 ` Michael S. Tsirkin
2019-11-19 17:01 ` Peter Xu
2019-11-19 12:27 ` [PATCH 1/2] intel_iommu: split the resevred fields arrays into two ones qi1.zhang
2019-11-19 12:28 ` [PATCH v2 " qi1.zhang
2019-11-19 16:06 ` Peter Xu
2019-11-22 8:10 ` Qi, Yadong
2019-11-19 12:28 ` [PATCH v2 0/2] TM field check failed qi1.zhang
2019-11-19 12:28 ` [PATCH v2 2/2] intel_iommu: TM field should not be in reserved bits qi1.zhang
2019-11-19 11:06 ` Michael S. Tsirkin
2019-11-19 12:27 ` [PATCH " qi1.zhang
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