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Wed, 20 Nov 2019 12:50:35 +0000 (UTC) Date: Wed, 20 Nov 2019 13:50:33 +0100 From: Igor Mammedov To: Tao Xu Subject: Re: [PATCH v16 12/14] hmat acpi: Build Memory Side Cache Information Structure(s) Message-ID: <20191120135033.78e0a20c@redhat.com> In-Reply-To: <20191115075352.17734-13-tao3.xu@intel.com> References: <20191115075352.17734-1-tao3.xu@intel.com> <20191115075352.17734-13-tao3.xu@intel.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-MC-Unique: ViadLZTNNTaZ7kkChctbxQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, thuth@redhat.com, ehabkost@redhat.com, mst@redhat.com, qemu-devel@nongnu.org, jingqi.liu@intel.com, fan.du@intel.com, mdroth@linux.vnet.ibm.com, Daniel Black , armbru@redhat.com, jonathan.cameron@huawei.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, 15 Nov 2019 15:53:50 +0800 Tao Xu wrote: > From: Liu Jingqi >=20 > This structure describes memory side cache information for memory > proximity domains if the memory side cache is present and the > physical device forms the memory side cache. > The software could use this information to effectively place > the data in memory to maximize the performance of the system > memory that use the memory side cache. >=20 > Reviewed-by: Daniel Black > Reviewed-by: Jonathan Cameron > Signed-off-by: Liu Jingqi > Signed-off-by: Tao Xu looks good, but I'll skip the patch this round since it will be changed by HMAT_Cache_Info removal in [9/14] > --- >=20 > Changes in v16: > - Use checks and assert to replace masks (Igor) > - Fields in Cache Attributes are promoted to uint32_t before > shifting (Igor) > - Drop cpu_to_le32() (Igor) >=20 > Changes in v13: > - rename level as cache_level > --- > hw/acpi/hmat.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 68 insertions(+), 1 deletion(-) >=20 > diff --git a/hw/acpi/hmat.c b/hw/acpi/hmat.c > index ed19ebed2f..2b4f760e0e 100644 > --- a/hw/acpi/hmat.c > +++ b/hw/acpi/hmat.c > @@ -144,14 +144,62 @@ static void build_hmat_lb(GArray *table_data, HMAT_= LB_Info *hmat_lb, > g_free(entry_list); > } > =20 > +/* ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure: Table 5-1= 47 */ > +static void build_hmat_cache(GArray *table_data, HMAT_Cache_Info *hmat_c= ache, > + uint8_t total_levels) > +{ > + /* > + * Cache Attributes: Bits [3:0] =E2=80=93 Total Cache Levels > + * for this Memory Proximity Domain > + */ > + uint32_t cache_attr =3D total_levels; > + > + /* Bits [7:4] : Cache Level described in this structure */ > + cache_attr |=3D (uint32_t) hmat_cache->level << 4; > + > + /* Bits [11:8] - Cache Associativity */ > + cache_attr |=3D (uint32_t) hmat_cache->associativity << 8; > + > + /* Bits [15:12] - Write Policy */ > + cache_attr |=3D (uint32_t) hmat_cache->write_policy << 12; > + > + /* Bits [31:16] - Cache Line size in bytes */ > + cache_attr |=3D (uint32_t) hmat_cache->line_size << 16; > + > + /* Type */ > + build_append_int_noprefix(table_data, 2, 2); > + /* Reserved */ > + build_append_int_noprefix(table_data, 0, 2); > + /* Length */ > + build_append_int_noprefix(table_data, 32, 4); > + /* Proximity Domain for the Memory */ > + build_append_int_noprefix(table_data, hmat_cache->proximity, 4); > + /* Reserved */ > + build_append_int_noprefix(table_data, 0, 4); > + /* Memory Side Cache Size */ > + build_append_int_noprefix(table_data, hmat_cache->size, 8); > + /* Cache Attributes */ > + build_append_int_noprefix(table_data, cache_attr, 4); > + /* Reserved */ > + build_append_int_noprefix(table_data, 0, 2); > + /* > + * Number of SMBIOS handles (n) > + * Linux kernel uses Memory Side Cache Information Structure > + * without SMBIOS entries for now, so set Number of SMBIOS handles > + * as 0. > + */ > + build_append_int_noprefix(table_data, 0, 2); > +} > + > /* Build HMAT sub table structures */ > static void hmat_build_table_structs(GArray *table_data, NumaState *numa= _state) > { > uint16_t flags; > uint32_t num_initiator =3D 0; > uint32_t initiator_list[MAX_NODES]; > - int i, hierarchy, type; > + int i, hierarchy, type, cache_level, total_levels; > HMAT_LB_Info *hmat_lb; > + HMAT_Cache_Info *hmat_cache; > =20 > for (i =3D 0; i < numa_state->num_nodes; i++) { > flags =3D 0; > @@ -185,6 +233,25 @@ static void hmat_build_table_structs(GArray *table_d= ata, NumaState *numa_state) > } > } > } > + > + /* > + * ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure: > + * Table 5-147 > + */ > + for (i =3D 0; i < numa_state->num_nodes; i++) { > + total_levels =3D 0; > + for (cache_level =3D 1; cache_level < HMAT_LB_LEVELS; cache_leve= l++) { > + if (numa_state->hmat_cache[i][cache_level]) { > + total_levels++; > + } > + } > + for (cache_level =3D 0; cache_level <=3D total_levels; cache_lev= el++) { > + hmat_cache =3D numa_state->hmat_cache[i][cache_level]; > + if (hmat_cache) { > + build_hmat_cache(table_data, hmat_cache, total_levels); > + } > + } > + } > } > =20 > void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *numa_= state)