Re: [PATCH v17 12/14] hmat acpi: Build Memory Side Cache Information Structure(s)

[Igor Mammedov <imammedo@redhat.com>]

On Fri, 22 Nov 2019 15:48:24 +0800
Tao Xu <tao3.xu@intel.com> wrote:

> From: Liu Jingqi <jingqi.liu@intel.com>
> 
> This structure describes memory side cache information for memory
> proximity domains if the memory side cache is present and the
> physical device forms the memory side cache.
> The software could use this information to effectively place
> the data in memory to maximize the performance of the system
> memory that use the memory side cache.
> 
> Reviewed-by: Daniel Black <daniel@linux.ibm.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

for the future reference,
You are not supposed to carry over Reviewed-by tags
if you do non trivial change to the patch.

> Signed-off-by: Liu Jingqi <jingqi.liu@intel.com>
> Signed-off-by: Tao Xu <tao3.xu@intel.com>

Reviewed-by: Igor Mammedov <imammedo@redhat.com>

> ---
> 
> No changes in v17.
> 
> Changes in v16:
>     - Use checks and assert to replace masks (Igor)
>     - Fields in Cache Attributes are promoted to uint32_t before
>       shifting (Igor)
>     - Drop cpu_to_le32() (Igor)
> 
> Changes in v13:
>     - rename level as cache_level
> ---
>  hw/acpi/hmat.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 68 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/acpi/hmat.c b/hw/acpi/hmat.c
> index e5ee8b4317..bb6adb0ccf 100644
> --- a/hw/acpi/hmat.c
> +++ b/hw/acpi/hmat.c
> @@ -143,14 +143,62 @@ static void build_hmat_lb(GArray *table_data, HMAT_LB_Info *hmat_lb,
>      g_free(entry_list);
>  }
>  
> +/* ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure: Table 5-147 */
> +static void build_hmat_cache(GArray *table_data, uint8_t total_levels,
> +                             NumaHmatCacheOptions *hmat_cache)
> +{
> +    /*
> +     * Cache Attributes: Bits [3:0] – Total Cache Levels
> +     * for this Memory Proximity Domain
> +     */
> +    uint32_t cache_attr = total_levels;
> +
> +    /* Bits [7:4] : Cache Level described in this structure */
> +    cache_attr |= (uint32_t) hmat_cache->level << 4;
> +
> +    /* Bits [11:8] - Cache Associativity */
> +    cache_attr |= (uint32_t) hmat_cache->assoc << 8;
> +
> +    /* Bits [15:12] - Write Policy */
> +    cache_attr |= (uint32_t) hmat_cache->policy << 12;
> +
> +    /* Bits [31:16] - Cache Line size in bytes */
> +    cache_attr |= (uint32_t) hmat_cache->line << 16;
> +
> +    /* Type */
> +    build_append_int_noprefix(table_data, 2, 2);
> +    /* Reserved */
> +    build_append_int_noprefix(table_data, 0, 2);
> +    /* Length */
> +    build_append_int_noprefix(table_data, 32, 4);
> +    /* Proximity Domain for the Memory */
> +    build_append_int_noprefix(table_data, hmat_cache->node_id, 4);
> +    /* Reserved */
> +    build_append_int_noprefix(table_data, 0, 4);
> +    /* Memory Side Cache Size */
> +    build_append_int_noprefix(table_data, hmat_cache->size, 8);
> +    /* Cache Attributes */
> +    build_append_int_noprefix(table_data, cache_attr, 4);
> +    /* Reserved */
> +    build_append_int_noprefix(table_data, 0, 2);
> +    /*
> +     * Number of SMBIOS handles (n)
> +     * Linux kernel uses Memory Side Cache Information Structure
> +     * without SMBIOS entries for now, so set Number of SMBIOS handles
> +     * as 0.
> +     */
> +    build_append_int_noprefix(table_data, 0, 2);
> +}
> +
>  /* Build HMAT sub table structures */
>  static void hmat_build_table_structs(GArray *table_data, NumaState *numa_state)
>  {
>      uint16_t flags;
>      uint32_t num_initiator = 0;
>      uint32_t initiator_list[MAX_NODES];
> -    int i, hierarchy, type;
> +    int i, hierarchy, type, cache_level, total_levels;
>      HMAT_LB_Info *hmat_lb;
> +    NumaHmatCacheOptions *hmat_cache;
>  
>      for (i = 0; i < numa_state->num_nodes; i++) {
>          flags = 0;
> @@ -184,6 +232,25 @@ static void hmat_build_table_structs(GArray *table_data, NumaState *numa_state)
>              }
>          }
>      }
> +
> +    /*
> +     * ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure:
> +     * Table 5-147
> +     */
> +    for (i = 0; i < numa_state->num_nodes; i++) {
> +        total_levels = 0;
> +        for (cache_level = 1; cache_level < HMAT_LB_LEVELS; cache_level++) {
> +            if (numa_state->hmat_cache[i][cache_level]) {
> +                total_levels++;
> +            }
> +        }
> +        for (cache_level = 0; cache_level <= total_levels; cache_level++) {
> +            hmat_cache = numa_state->hmat_cache[i][cache_level];
> +            if (hmat_cache) {
> +                build_hmat_cache(table_data, total_levels, hmat_cache);
> +            }
> +        }
> +    }
>  }
>  
>  void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *numa_state)