From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.3 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A0AAC432C3 for ; Sun, 24 Nov 2019 05:04:40 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6399C2073F for ; Sun, 24 Nov 2019 05:04:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="qt/wp4l4" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6399C2073F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:33882 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iYk4d-00051y-2w for qemu-devel@archiver.kernel.org; Sun, 24 Nov 2019 00:04:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60432) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iYk37-0003S3-M1 for qemu-devel@nongnu.org; Sun, 24 Nov 2019 00:03:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iYk36-0007VA-CM for qemu-devel@nongnu.org; Sun, 24 Nov 2019 00:03:05 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:35346) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iYk36-0007Ug-6D for qemu-devel@nongnu.org; Sun, 24 Nov 2019 00:03:04 -0500 Received: by mail-wr1-x435.google.com with SMTP id s5so13405417wrw.2 for ; Sat, 23 Nov 2019 21:03:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sXgUfb/k+VBdpZH8pPaVua4ZrgGvG7BUVKKWHWPW/NE=; b=qt/wp4l4BNSMJRh6Z2mg8QKdq4LQJMQbQNqFdUhD6Z1DidPZqVk3t76QBESL0Li3my 0OvPrJMYzHhNEEx2CF0Cf6v9RjWz3VFwlng4FeJLSxgOH5XDbuwlaHxi2own1D1nleSK hMP/T3me0ryoK0tM8j6vXUug+LnvT6c4+xGm2zFtHXQJ746tg+qvAGAKTIE1M4PC3oKW VTlNpURlUnxV2n1HMQtTPONGvkjkcEcjqeQcp0vs1PqUJ4BF92Aus1qdI88f19PqzkwP Ss1GZ7EXji3l64D0W0hysAYnGBvWm2w3TRe0MPoxB06NqMzxrWh/DGytcvsSwg7OZyJ7 2YPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sXgUfb/k+VBdpZH8pPaVua4ZrgGvG7BUVKKWHWPW/NE=; b=GPiJJUVMg+FIT+OCWDA99HbCtCin0dR6z4WLeh35Gal7Vrk2agGacV/eFApaQZkRlh J07H4ikEY2GM/4+G6r9KhPfIILRQZYMCkK0PDl7tZpHylzqzzt+4ppUBlzdfy061GatY 7GYRT+X7QauxCeV29dO05oM966mx/TGyrYLxJImRhXKowv76inXuKm8vUVEzDDp5SmW3 k28/2RKWsI1iQQtBHpf/sDszrZ4Ty4lDTDgOP1V7x5wJ6xnXMwNqr8h3YbpTgbMmpewy 9kwx7oc4Z2yopPnDlO8lgQt3QmNwOIeuhVvHG38BtLkZLJsyBD6sxAfWFBc46Q3QheDR 8j1Q== X-Gm-Message-State: APjAAAWznhx9mJSEGZL1/zmAMXHwEHWZe9KEDg6IEXugBRlG7dO/jVBA v5CbNeW3FY99pyW7S0kgD+/te7MIcZVzNQqt X-Google-Smtp-Source: APXvYqyFgM5ySUI4x3Ws1I+Dc/U6fReTZt2gfG9Xj89Mss8d3HFPULEkhvc4PRXH2ieiW1xiMdhUzQ== X-Received: by 2002:a5d:5391:: with SMTP id d17mr26626690wrv.382.1574571782833; Sat, 23 Nov 2019 21:03:02 -0800 (PST) Received: from 8c859074c0ff.ant.amazon.com.com (bzq-79-178-10-38.red.bezeqint.net. [79.178.10.38]) by smtp.gmail.com with ESMTPSA id t185sm4173976wmf.45.2019.11.23.21.03.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 23 Nov 2019 21:03:02 -0800 (PST) From: Michael Rolnik To: qemu-devel@nongnu.org Subject: [PATCH v36 04/17] target/avr: Add instruction translation - Registers definition Date: Sun, 24 Nov 2019 07:02:12 +0200 Message-Id: <20191124050225.30351-5-mrolnik@gmail.com> X-Mailer: git-send-email 2.17.2 (Apple Git-113) In-Reply-To: <20191124050225.30351-1-mrolnik@gmail.com> References: <20191124050225.30351-1-mrolnik@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::435 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, Michael Rolnik , richard.henderson@linaro.org, dovgaluk@ispras.ru, imammedo@redhat.com, philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Michael Rolnik --- target/avr/translate.c | 132 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 132 insertions(+) create mode 100644 target/avr/translate.c diff --git a/target/avr/translate.c b/target/avr/translate.c new file mode 100644 index 0000000000..53c9892a60 --- /dev/null +++ b/target/avr/translate.c @@ -0,0 +1,132 @@ +/* + * QEMU AVR CPU + * + * Copyright (c) 2019 Michael Rolnik + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * + */ + +#include "qemu/osdep.h" +#include "qemu/qemu-print.h" +#include "tcg/tcg.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "disas/disas.h" +#include "tcg-op.h" +#include "exec/cpu_ldst.h" +#include "exec/helper-proto.h" +#include "exec/helper-gen.h" +#include "exec/log.h" +#include "exec/gdbstub.h" +#include "exec/translator.h" +#include "exec/gen-icount.h" + +/* + * Define if you want a BREAK instruction translated to a breakpoint + * Active debugging connection is assumed + * This is for + * https://github.com/seharris/qemu-avr-tests/tree/master/instruction-tests + * tests + */ +#undef BREAKPOINT_ON_BREAK + +static TCGv cpu_pc; + +static TCGv cpu_Cf; +static TCGv cpu_Zf; +static TCGv cpu_Nf; +static TCGv cpu_Vf; +static TCGv cpu_Sf; +static TCGv cpu_Hf; +static TCGv cpu_Tf; +static TCGv cpu_If; + +static TCGv cpu_rampD; +static TCGv cpu_rampX; +static TCGv cpu_rampY; +static TCGv cpu_rampZ; + +static TCGv cpu_r[NO_CPU_REGISTERS]; +static TCGv cpu_eind; +static TCGv cpu_sp; + +static TCGv cpu_skip; + +static const char reg_names[NO_CPU_REGISTERS][8] = { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", +}; +#define REG(x) (cpu_r[x]) + +enum { + DISAS_EXIT = DISAS_TARGET_0, /* We want return to the cpu main loop. */ + DISAS_LOOKUP = DISAS_TARGET_1, /* We have a variable condition exit. */ + DISAS_CHAIN = DISAS_TARGET_2, /* We have a single condition exit. */ +}; + +typedef struct DisasContext DisasContext; + +/* This is the state at translation time. */ +struct DisasContext { + TranslationBlock *tb; + + CPUAVRState *env; + CPUState *cs; + + target_long npc; + uint32_t opcode; + + /* Routine used to access memory */ + int memidx; + int bstate; + int singlestep; + + TCGv skip_var0; + TCGv skip_var1; + TCGCond skip_cond; + bool free_skip_var0; +}; + +static int to_A(DisasContext *ctx, int indx) { return 16 + (indx % 16); } +static int to_B(DisasContext *ctx, int indx) { return 16 + (indx % 8); } +static int to_C(DisasContext *ctx, int indx) { return 24 + (indx % 4) * 2; } +static int to_D(DisasContext *ctx, int indx) { return (indx % 16) * 2; } + +static uint16_t next_word(DisasContext *ctx) +{ + return cpu_lduw_code(ctx->env, ctx->npc++ * 2); +} + +static int append_16(DisasContext *ctx, int x) +{ + return x << 16 | next_word(ctx); +} + + +static bool avr_have_feature(DisasContext *ctx, int feature) +{ + if (!avr_feature(ctx->env, feature)) { + gen_helper_unsupported(cpu_env); + ctx->bstate = DISAS_NORETURN; + return false; + } + return true; +} + +static bool decode_insn(DisasContext *ctx, uint16_t insn); +#include "decode_insn.inc.c" + -- 2.17.2 (Apple Git-113)