From: Peter Xu <peterx@redhat.com>
To: yadong.qi@intel.com
Cc: qi1.zhang@intel.com, ehabkost@redhat.com, mst@redhat.com,
qemu-devel@nongnu.org, pbonzini@redhat.com, rth@twiddle.net
Subject: Re: [PATCH v3 0/2] Refine Second-Level Paging Entries reserved fields checking
Date: Sun, 24 Nov 2019 22:08:59 -0500 [thread overview]
Message-ID: <20191125030859.GE30539@xz-x1> (raw)
In-Reply-To: <20191125003321.5669-1-yadong.qi@intel.com>
On Mon, Nov 25, 2019 at 08:33:19AM +0800, yadong.qi@intel.com wrote:
> From: "Qi, Yadong" <yadong.qi@intel.com>
>
> The following patches are to refine/fix issues of reserved fields checking logic
> of Second-Level Paging Entries of VT-d:
> - split the resevred fields arrays into two ones,
> - large page only effect for L2(2M) and L3(1G), so remove
> checking of L1 and L4 for large page,
> - when dt is supported, TM filed should not be Reserved(0).
>
> Changes in v3:
> - large page only effect for L2(2M) and L3(1G), so remove
> checking of L1 and L4 for large page
Reviewed-by: Peter Xu <peterx@redhat.com>
Thanks,
--
Peter Xu
next prev parent reply other threads:[~2019-11-25 3:10 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-25 0:33 [PATCH v3 0/2] Refine Second-Level Paging Entries reserved fields checking yadong.qi
2019-11-25 0:33 ` [PATCH v3 1/2] intel_iommu: refine SL-PEs " yadong.qi
2019-11-25 0:33 ` [PATCH v3 2/2] intel_iommu: TM field should not be in reserved bits yadong.qi
2019-11-25 3:08 ` Peter Xu [this message]
-- strict thread matches above, loose matches on Subject: below --
2019-11-25 0:21 [PATCH v3 0/2] Refine Second-Level Paging Entries reserved fields checking yadong.qi
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