* [PULL 1/3] virtio-input: fix memory leak on unrealize
2019-11-25 8:44 [PULL 0/3] virtio, pc: fixes Michael S. Tsirkin
@ 2019-11-25 8:44 ` Michael S. Tsirkin
2019-11-25 8:44 ` [PULL 2/3] intel_iommu: refine SL-PEs reserved fields checking Michael S. Tsirkin
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Michael S. Tsirkin @ 2019-11-25 8:44 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Gerd Hoffmann, Marc-André Lureau
From: Marc-André Lureau <marcandre.lureau@redhat.com>
Spotted by ASAN + minor stylistic change.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20191121095649.25453-1-marcandre.lureau@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/input/virtio-input.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/input/virtio-input.c b/hw/input/virtio-input.c
index 51617a5885..ec54e46ad6 100644
--- a/hw/input/virtio-input.c
+++ b/hw/input/virtio-input.c
@@ -275,6 +275,7 @@ static void virtio_input_finalize(Object *obj)
g_free(vinput->queue);
}
+
static void virtio_input_device_unrealize(DeviceState *dev, Error **errp)
{
VirtIOInputClass *vic = VIRTIO_INPUT_GET_CLASS(dev);
@@ -288,6 +289,8 @@ static void virtio_input_device_unrealize(DeviceState *dev, Error **errp)
return;
}
}
+ virtio_del_queue(vdev, 0);
+ virtio_del_queue(vdev, 1);
virtio_cleanup(vdev);
}
--
MST
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PULL 2/3] intel_iommu: refine SL-PEs reserved fields checking
2019-11-25 8:44 [PULL 0/3] virtio, pc: fixes Michael S. Tsirkin
2019-11-25 8:44 ` [PULL 1/3] virtio-input: fix memory leak on unrealize Michael S. Tsirkin
@ 2019-11-25 8:44 ` Michael S. Tsirkin
2019-11-25 8:44 ` [PULL 3/3] intel_iommu: TM field should not be in reserved bits Michael S. Tsirkin
2019-11-25 16:25 ` [PULL 0/3] virtio, pc: fixes Peter Maydell
3 siblings, 0 replies; 5+ messages in thread
From: Michael S. Tsirkin @ 2019-11-25 8:44 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Eduardo Habkost, Qi, Qi, Peter Xu, Zhang,
Paolo Bonzini, Qi, Yadong, Richard Henderson
From: "Qi, Yadong" <yadong.qi@intel.com>
1. split the resevred fields arrays into two ones,
2. large page only effect for L2(2M) and L3(1G), so
remove checking of L1 and L4 for large page.
Signed-off-by: Zhang, Qi <qi1.zhang@intel.com>
Signed-off-by: Qi, Yadong <yadong.qi@intel.com>
Message-Id: <20191125003321.5669-2-yadong.qi@intel.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/intel_iommu.c | 37 ++++++++++++++++++----------------
hw/i386/intel_iommu_internal.h | 5 +----
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 14e4e6ad62..feb9e55f87 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -910,19 +910,23 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUState *s,
/*
* Rsvd field masks for spte:
- * Index [1] to [4] 4k pages
- * Index [5] to [8] large pages
+ * vtd_spte_rsvd 4k pages
+ * vtd_spte_rsvd_large large pages
*/
-static uint64_t vtd_paging_entry_rsvd_field[9];
+static uint64_t vtd_spte_rsvd[5];
+static uint64_t vtd_spte_rsvd_large[5];
static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
{
- if (slpte & VTD_SL_PT_PAGE_SIZE_MASK) {
- /* Maybe large page */
- return slpte & vtd_paging_entry_rsvd_field[level + 4];
- } else {
- return slpte & vtd_paging_entry_rsvd_field[level];
+ uint64_t rsvd_mask = vtd_spte_rsvd[level];
+
+ if ((level == VTD_SL_PD_LEVEL || level == VTD_SL_PDP_LEVEL) &&
+ (slpte & VTD_SL_PT_PAGE_SIZE_MASK)) {
+ /* large page */
+ rsvd_mask = vtd_spte_rsvd_large[level];
}
+
+ return slpte & rsvd_mask;
}
/* Find the VTD address space associated with a given bus number */
@@ -3549,15 +3553,14 @@ static void vtd_init(IntelIOMMUState *s)
/*
* Rsvd field masks for spte
*/
- vtd_paging_entry_rsvd_field[0] = ~0ULL;
- vtd_paging_entry_rsvd_field[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[5] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[6] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[7] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[8] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[0] = ~0ULL;
+ vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
+
+ vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
if (x86_iommu_ir_supported(x86_iommu)) {
s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index c1235a7063..1654f746bc 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -395,14 +395,11 @@ typedef union VTDInvDesc VTDInvDesc;
(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
#define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \
(0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
-#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw) \
- (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
+
#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \
(0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \
(0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
-#define VTD_SPTE_LPAGE_L4_RSVD_MASK(aw) \
- (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
/* Information about page-selective IOTLB invalidate */
struct VTDIOTLBPageInvInfo {
--
MST
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PULL 3/3] intel_iommu: TM field should not be in reserved bits
2019-11-25 8:44 [PULL 0/3] virtio, pc: fixes Michael S. Tsirkin
2019-11-25 8:44 ` [PULL 1/3] virtio-input: fix memory leak on unrealize Michael S. Tsirkin
2019-11-25 8:44 ` [PULL 2/3] intel_iommu: refine SL-PEs reserved fields checking Michael S. Tsirkin
@ 2019-11-25 8:44 ` Michael S. Tsirkin
2019-11-25 16:25 ` [PULL 0/3] virtio, pc: fixes Peter Maydell
3 siblings, 0 replies; 5+ messages in thread
From: Michael S. Tsirkin @ 2019-11-25 8:44 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Eduardo Habkost, Qi, Qi, Peter Xu, Zhang,
Paolo Bonzini, Qi, Yadong, Richard Henderson
From: "Qi, Yadong" <yadong.qi@intel.com>
When dt is supported, TM field should not be Reserved(0).
Refer to VT-d Spec 9.8
Signed-off-by: Zhang, Qi <qi1.zhang@intel.com>
Signed-off-by: Qi, Yadong <yadong.qi@intel.com>
Message-Id: <20191125003321.5669-3-yadong.qi@intel.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/intel_iommu.c | 9 ++++++---
hw/i386/intel_iommu_internal.h | 13 ++++++++++---
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index feb9e55f87..43c94b993b 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3554,13 +3554,16 @@ static void vtd_init(IntelIOMMUState *s)
* Rsvd field masks for spte
*/
vtd_spte_rsvd[0] = ~0ULL;
- vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
- vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
- vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
+ vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
if (x86_iommu_ir_supported(x86_iommu)) {
s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 1654f746bc..edcf9fc9bb 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -387,7 +387,9 @@ typedef union VTDInvDesc VTDInvDesc;
#define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8
/* Rsvd field masks for spte */
-#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \
+#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \
+ dt_supported ? \
+ (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
#define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \
(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
@@ -396,9 +398,13 @@ typedef union VTDInvDesc VTDInvDesc;
#define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \
(0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
-#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \
+#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, dt_supported) \
+ dt_supported ? \
+ (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
-#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \
+#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, dt_supported) \
+ dt_supported ? \
+ (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
/* Information about page-selective IOTLB invalidate */
@@ -503,5 +509,6 @@ typedef struct VTDRootEntry VTDRootEntry;
#define VTD_SL_W (1ULL << 1)
#define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw))
#define VTD_SL_IGN_COM 0xbff0000000000000ULL
+#define VTD_SL_TM (1ULL << 62)
#endif
--
MST
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PULL 0/3] virtio, pc: fixes
2019-11-25 8:44 [PULL 0/3] virtio, pc: fixes Michael S. Tsirkin
` (2 preceding siblings ...)
2019-11-25 8:44 ` [PULL 3/3] intel_iommu: TM field should not be in reserved bits Michael S. Tsirkin
@ 2019-11-25 16:25 ` Peter Maydell
3 siblings, 0 replies; 5+ messages in thread
From: Peter Maydell @ 2019-11-25 16:25 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: QEMU Developers
On Mon, 25 Nov 2019 at 08:44, Michael S. Tsirkin <mst@redhat.com> wrote:
>
> The following changes since commit 2061735ff09f9d5e67c501a96227b470e7de69b1:
>
> Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2019-11-21 17:18:40 +0000)
>
> are available in the Git repository at:
>
> git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstream
>
> for you to fetch changes up to e48929c787ed0ebed87877c97ac90c3a47ef7dda:
>
> intel_iommu: TM field should not be in reserved bits (2019-11-25 03:42:58 -0500)
>
> ----------------------------------------------------------------
> virtio, pc: fixes
>
> More small bugfixes.
>
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/4.2
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 5+ messages in thread