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[79.176.6.42]) by smtp.gmail.com with ESMTPSA id k7sm3031437qkf.40.2019.11.25.00.44.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Nov 2019 00:44:47 -0800 (PST) Date: Mon, 25 Nov 2019 03:44:42 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Subject: [PULL 3/3] intel_iommu: TM field should not be in reserved bits Message-ID: <20191125084403.324866-4-mst@redhat.com> References: <20191125084403.324866-1-mst@redhat.com> MIME-Version: 1.0 In-Reply-To: <20191125084403.324866-1-mst@redhat.com> X-Mailer: git-send-email 2.22.0.678.g13338e74b8 X-Mutt-Fcc: =sent X-MC-Unique: QNAo_V4nOse9nqTRLey8zA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Eduardo Habkost , Qi , Qi@redhat.com, Peter Xu , Zhang@redhat.com, Paolo Bonzini , "Qi, Yadong" , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: "Qi, Yadong" When dt is supported, TM field should not be Reserved(0). Refer to VT-d Spec 9.8 Signed-off-by: Zhang, Qi Signed-off-by: Qi, Yadong Message-Id: <20191125003321.5669-3-yadong.qi@intel.com> Reviewed-by: Peter Xu Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/intel_iommu.c | 9 ++++++--- hw/i386/intel_iommu_internal.h | 13 ++++++++++--- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index feb9e55f87..43c94b993b 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3554,13 +3554,16 @@ static void vtd_init(IntelIOMMUState *s) * Rsvd field masks for spte */ vtd_spte_rsvd[0] =3D ~0ULL; - vtd_spte_rsvd[1] =3D VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd[1] =3D VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits, + x86_iommu->dt_supported)= ; vtd_spte_rsvd[2] =3D VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits); vtd_spte_rsvd[3] =3D VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits); vtd_spte_rsvd[4] =3D VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits); =20 - vtd_spte_rsvd_large[2] =3D VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits); - vtd_spte_rsvd_large[3] =3D VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd_large[2] =3D VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits, + x86_iommu->dt_sup= ported); + vtd_spte_rsvd_large[3] =3D VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits, + x86_iommu->dt_sup= ported); =20 if (x86_iommu_ir_supported(x86_iommu)) { s->ecap |=3D VTD_ECAP_IR | VTD_ECAP_MHMV; diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.= h index 1654f746bc..edcf9fc9bb 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -387,7 +387,9 @@ typedef union VTDInvDesc VTDInvDesc; #define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8 =20 /* Rsvd field masks for spte */ -#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \ +#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \ + dt_supported ? \ + (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \ (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) #define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \ (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) @@ -396,9 +398,13 @@ typedef union VTDInvDesc VTDInvDesc; #define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \ (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) =20 -#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \ +#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, dt_supported) \ + dt_supported ? \ + (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) := \ (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) -#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \ +#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, dt_supported) \ + dt_supported ? \ + (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM))= : \ (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) =20 /* Information about page-selective IOTLB invalidate */ @@ -503,5 +509,6 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_SL_W (1ULL << 1) #define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(= aw)) #define VTD_SL_IGN_COM 0xbff0000000000000ULL +#define VTD_SL_TM (1ULL << 62) =20 #endif --=20 MST