From: David Gibson <david@gibson.dropbear.id.au>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: qemu-ppc@nongnu.org, Greg Kurz <groug@kaod.org>, qemu-devel@nongnu.org
Subject: Re: [PATCH 07/13] ppc/pnv: Introduce PnvChipClass::intc_print_info() method
Date: Mon, 16 Dec 2019 12:28:10 +1100 [thread overview]
Message-ID: <20191216012810.GA3256@umbus.fritz.box> (raw)
In-Reply-To: <4039344f-eb1c-3ea3-1055-09aeffd28ce7@kaod.org>
[-- Attachment #1: Type: text/plain, Size: 7403 bytes --]
On Fri, Dec 13, 2019 at 02:00:53PM +0100, Cédric Le Goater wrote:
> On 13/12/2019 13:00, Greg Kurz wrote:
> > The pnv_pic_print_info() callback checks the type of the chip in order
> > to forward to the request appropriate interrupt controller. This can
> > be achieved with QOM. Introduce a method for this in the base chip class
> > and implement it in child classes.
> >
> > This also prepares ground for the upcoming interrupt controller of POWER10
> > chips.
> >
> > Signed-off-by: Greg Kurz <groug@kaod.org>
>
>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
>
> One comment below.
>
> > ---
> > hw/ppc/pnv.c | 30 +++++++++++++++++++++++++-----
> > include/hw/ppc/pnv.h | 1 +
> > 2 files changed, 26 insertions(+), 5 deletions(-)
> >
> > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> > index efc00f4cb67a..2a53e99bda2e 100644
> > --- a/hw/ppc/pnv.c
> > +++ b/hw/ppc/pnv.c
> > @@ -832,6 +832,12 @@ static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
> > pnv_cpu->intc = NULL;
> > }
> >
> > +static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
> > + Monitor *mon)
> > +{
> > + icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
> > +}
> > +
> > /*
> > * 0:48 Reserved - Read as zeroes
> > * 49:52 Node ID
> > @@ -889,6 +895,12 @@ static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
> > pnv_cpu->intc = NULL;
> > }
> >
> > +static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
> > + Monitor *mon)
> > +{
> > + xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
> > +}
> > +
> > static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
> > Error **errp)
> > {
> > @@ -910,6 +922,11 @@ static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
> > pnv_cpu->intc = NULL;
> > }
> >
> > +static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
> > + Monitor *mon)
> > +{
> > +}
> > +
> > /*
> > * Allowed core identifiers on a POWER8 Processor Chip :
> > *
> > @@ -1086,6 +1103,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
> > k->intc_create = pnv_chip_power8_intc_create;
> > k->intc_reset = pnv_chip_power8_intc_reset;
> > k->intc_destroy = pnv_chip_power8_intc_destroy;
> > + k->intc_print_info = pnv_chip_power8_intc_print_info;
> > k->isa_create = pnv_chip_power8_isa_create;
> > k->dt_populate = pnv_chip_power8_dt_populate;
> > k->pic_print_info = pnv_chip_power8_pic_print_info;
> > @@ -1107,6 +1125,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
> > k->intc_create = pnv_chip_power8_intc_create;
> > k->intc_reset = pnv_chip_power8_intc_reset;
> > k->intc_destroy = pnv_chip_power8_intc_destroy;
> > + k->intc_print_info = pnv_chip_power8_intc_print_info;
> > k->isa_create = pnv_chip_power8_isa_create;
> > k->dt_populate = pnv_chip_power8_dt_populate;
> > k->pic_print_info = pnv_chip_power8_pic_print_info;
> > @@ -1128,6 +1147,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
> > k->intc_create = pnv_chip_power8_intc_create;
> > k->intc_reset = pnv_chip_power8_intc_reset;
> > k->intc_destroy = pnv_chip_power8_intc_destroy;
> > + k->intc_print_info = pnv_chip_power8_intc_print_info;
> > k->isa_create = pnv_chip_power8nvl_isa_create;
> > k->dt_populate = pnv_chip_power8_dt_populate;
> > k->pic_print_info = pnv_chip_power8_pic_print_info;
> > @@ -1299,6 +1319,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
> > k->intc_create = pnv_chip_power9_intc_create;
> > k->intc_reset = pnv_chip_power9_intc_reset;
> > k->intc_destroy = pnv_chip_power9_intc_destroy;
> > + k->intc_print_info = pnv_chip_power9_intc_print_info;
> > k->isa_create = pnv_chip_power9_isa_create;
> > k->dt_populate = pnv_chip_power9_dt_populate;
> > k->pic_print_info = pnv_chip_power9_pic_print_info;
> > @@ -1379,6 +1400,7 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
> > k->intc_create = pnv_chip_power10_intc_create;
> > k->intc_reset = pnv_chip_power10_intc_reset;
> > k->intc_destroy = pnv_chip_power10_intc_destroy;
> > + k->intc_print_info = pnv_chip_power10_intc_print_info;
> > k->isa_create = pnv_chip_power10_isa_create;
> > k->dt_populate = pnv_chip_power10_dt_populate;
> > k->pic_print_info = pnv_chip_power10_pic_print_info;
> > @@ -1575,11 +1597,9 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj,
> > CPU_FOREACH(cs) {
> > PowerPCCPU *cpu = POWERPC_CPU(cs);
> >
> > - if (pnv_chip_is_power9(pnv->chips[0])) {
> > - xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
> > - } else {
> > - icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
> > - }
> > + /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
>
> May be we should introduce a helper such as :
>
> int pnv_chip_cpu_foreach(PnvChip *chip,
> int (*doit)(PnvChip *chip, PowerPCCPU *cpu, void *opaque), void *opaque)
> {
> int i, j;
> int ret = 0;
>
> for (i = 0; i < chip->nr_cores; i++) {
> PnvCore *pc = chip->cores[i];
> CPUCore *cc = CPU_CORE(pc);
>
> for (j = 0; j < cc->nr_threads; j++) {
> PowerPCCPU *cpu = pc->threads[j];
> ret = doit(chip, cpu, opaque);
> if (ret) {
> break;
> }
> }
> }
> return ret;
> }
What I'd actually like to work towards is just having the interrupt
controllers themselves advertize TYPE_INTERRUPT_STATS_PROVIDER and not
needing anything specific at the machine level to locate them, just
let the generic code in hmp_info_pic handle it.
But this patch is fine in the meantime.
>
> > + PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu,
> > + mon);
> > }
> >
> > for (i = 0; i < pnv->num_chips; i++) {
> > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> > index c213bdd5ecd3..7d2402784d4b 100644
> > --- a/include/hw/ppc/pnv.h
> > +++ b/include/hw/ppc/pnv.h
> > @@ -133,6 +133,7 @@ typedef struct PnvChipClass {
> > void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
> > void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
> > void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
> > + void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon);
> > ISABus *(*isa_create)(PnvChip *chip, Error **errp);
> > void (*dt_populate)(PnvChip *chip, void *fdt);
> > void (*pic_print_info)(PnvChip *chip, Monitor *mon);
> >
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
next prev parent reply other threads:[~2019-12-16 1:35 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-13 11:59 [PATCH 00/13] ppc/pnv: Get rid of chip_type attributes Greg Kurz
2019-12-13 11:59 ` [PATCH 01/13] ppc: Drop useless extern annotation for functions Greg Kurz
2019-12-13 11:59 ` [PATCH 02/13] ppc/pnv: Introduce PnvPsiClass::compat Greg Kurz
2019-12-13 12:42 ` Cédric Le Goater
2019-12-13 11:59 ` [PATCH 03/13] ppc/pnv: Drop PnvPsiClass::chip_type Greg Kurz
2019-12-13 12:43 ` Cédric Le Goater
2019-12-13 11:59 ` [PATCH 04/13] ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compat Greg Kurz
2019-12-13 12:44 ` Cédric Le Goater
2019-12-16 18:07 ` Greg Kurz
2019-12-17 0:00 ` David Gibson
2019-12-13 11:59 ` [PATCH 05/13] ppc/pnv: Introduce PnvMachineClass::dt_power_mgt() Greg Kurz
2019-12-13 12:44 ` Cédric Le Goater
2019-12-13 12:00 ` [PATCH 06/13] ppc/pnv: Drop pnv_is_power9() and pnv_is_power10() helpers Greg Kurz
2019-12-13 12:59 ` Cédric Le Goater
2019-12-13 12:00 ` [PATCH 07/13] ppc/pnv: Introduce PnvChipClass::intc_print_info() method Greg Kurz
2019-12-13 13:00 ` Cédric Le Goater
2019-12-16 1:28 ` David Gibson [this message]
2019-12-16 7:54 ` Cédric Le Goater
2019-12-13 12:00 ` [PATCH 08/13] ppc/pnv: Introduce PnvChipClass::xscom_core_base() method Greg Kurz
2019-12-13 13:01 ` Cédric Le Goater
2019-12-13 12:00 ` [PATCH 09/13] ppc/pnv: Pass XSCOM base address and address size to pnv_dt_xscom() Greg Kurz
2019-12-13 13:03 ` Cédric Le Goater
2019-12-13 12:00 ` [PATCH 10/13] ppc/pnv: Pass content of the "compatible" property " Greg Kurz
2019-12-13 13:03 ` Cédric Le Goater
2019-12-13 12:00 ` [PATCH 11/13] ppc/pnv: Drop pnv_chip_is_power9() and pnv_chip_is_power10() helpers Greg Kurz
2019-12-13 13:05 ` Cédric Le Goater
2019-12-13 12:00 ` [PATCH 12/13] ppc/pnv: Introduce PnvChipClass::xscom_pcba() method Greg Kurz
2019-12-13 13:06 ` Cédric Le Goater
2019-12-16 1:32 ` David Gibson
2019-12-13 12:00 ` [PATCH 13/13] ppc/pnv: Drop PnvChipClass::type Greg Kurz
2019-12-13 13:06 ` Cédric Le Goater
2019-12-16 1:34 ` [PATCH 00/13] ppc/pnv: Get rid of chip_type attributes David Gibson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20191216012810.GA3256@umbus.fritz.box \
--to=david@gibson.dropbear.id.au \
--cc=clg@kaod.org \
--cc=groug@kaod.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).