qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org,
	groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org,
	David Gibson <david@gibson.dropbear.id.au>
Subject: [PULL 29/88] ppc/pnv: Instantiate cores separately
Date: Tue, 17 Dec 2019 15:42:23 +1100	[thread overview]
Message-ID: <20191217044322.351838-30-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au>

From: Greg Kurz <groug@kaod.org>

Allocating a big void * array to store multiple objects isn't a
recommended practice for various reasons:
 - no compile time type checking
 - potential dangling pointers if a reference on an individual is
  taken and the array is freed later on
 - duplicate boiler plate everywhere the array is browsed through

Allocate an array of pointers and populate it instead.

Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-4-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 hw/ppc/pnv.c         | 30 ++++++++++++------------------
 include/hw/ppc/pnv.h |  2 +-
 2 files changed, 13 insertions(+), 19 deletions(-)

diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index f0adb06c8d..d899c83e52 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -280,14 +280,12 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
 
 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
 {
-    const char *typename = pnv_chip_core_typename(chip);
-    size_t typesize = object_type_get_instance_size(typename);
     int i;
 
     pnv_dt_xscom(chip, fdt, 0);
 
     for (i = 0; i < chip->nr_cores; i++) {
-        PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
+        PnvCore *pnv_core = chip->cores[i];
 
         pnv_dt_core(chip, pnv_core, fdt);
 
@@ -302,14 +300,12 @@ static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
 
 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
 {
-    const char *typename = pnv_chip_core_typename(chip);
-    size_t typesize = object_type_get_instance_size(typename);
     int i;
 
     pnv_dt_xscom(chip, fdt, 0);
 
     for (i = 0; i < chip->nr_cores; i++) {
-        PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
+        PnvCore *pnv_core = chip->cores[i];
 
         pnv_dt_core(chip, pnv_core, fdt);
     }
@@ -913,8 +909,6 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
  {
     PnvChip *chip = PNV_CHIP(chip8);
     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
-    const char *typename = pnv_chip_core_typename(chip);
-    size_t typesize = object_type_get_instance_size(typename);
     int i, j;
     char *name;
     XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
@@ -928,7 +922,7 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
 
     /* Map the ICP registers for each thread */
     for (i = 0; i < chip->nr_cores; i++) {
-        PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
+        PnvCore *pnv_core = chip->cores[i];
         int core_hwid = CPU_CORE(pnv_core)->core_id;
 
         for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
@@ -1108,8 +1102,6 @@ static void pnv_chip_power9_instance_init(Object *obj)
 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
 {
     PnvChip *chip = PNV_CHIP(chip9);
-    const char *typename = pnv_chip_core_typename(chip);
-    size_t typesize = object_type_get_instance_size(typename);
     int i;
 
     chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
@@ -1118,7 +1110,7 @@ static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
     for (i = 0; i < chip9->nr_quads; i++) {
         char eq_name[32];
         PnvQuad *eq = &chip9->quads[i];
-        PnvCore *pnv_core = PNV_CORE(chip->cores + (i * 4) * typesize);
+        PnvCore *pnv_core = chip->cores[i * 4];
         int core_id = CPU_CORE(pnv_core)->core_id;
 
         snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
@@ -1290,7 +1282,6 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
     Error *error = NULL;
     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
     const char *typename = pnv_chip_core_typename(chip);
-    size_t typesize = object_type_get_instance_size(typename);
     int i, core_hwid;
 
     if (!object_class_by_name(typename)) {
@@ -1305,21 +1296,24 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
         return;
     }
 
-    chip->cores = g_malloc0(typesize * chip->nr_cores);
+    chip->cores = g_new0(PnvCore *, chip->nr_cores);
 
     for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
              && (i < chip->nr_cores); core_hwid++) {
         char core_name[32];
-        void *pnv_core = chip->cores + i * typesize;
+        PnvCore *pnv_core;
         uint64_t xscom_core_base;
 
         if (!(chip->cores_mask & (1ull << core_hwid))) {
             continue;
         }
 
+        pnv_core = PNV_CORE(object_new(typename));
+
         snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
-        object_initialize_child(OBJECT(chip), core_name, pnv_core, typesize,
-                                typename, &error_fatal, NULL);
+        object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
+                                  &error_abort);
+        chip->cores[i] = pnv_core;
         object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads",
                                 &error_fatal);
         object_property_set_int(OBJECT(pnv_core), core_hwid,
@@ -1340,7 +1334,7 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
         }
 
         pnv_xscom_add_subregion(chip, xscom_core_base,
-                                &PNV_CORE(pnv_core)->xscom_regs);
+                                &pnv_core->xscom_regs);
         i++;
     }
 }
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 90f1343ed0..03cb429f21 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -56,7 +56,7 @@ typedef struct PnvChip {
 
     uint32_t     nr_cores;
     uint64_t     cores_mask;
-    void         *cores;
+    PnvCore      **cores;
 
     MemoryRegion xscom_mmio;
     MemoryRegion xscom;
-- 
2.23.0



  parent reply	other threads:[~2019-12-17  5:10 UTC|newest]

Thread overview: 94+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-17  4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
2019-12-17  4:41 ` [PULL 01/88] ppc/pnv: Add a PNOR model David Gibson
2020-01-07 14:43   ` Peter Maydell
2020-01-07 16:26     ` Cédric Le Goater
2019-12-17  4:41 ` [PULL 02/88] ppc/pnv: Add a "/qemu" device tree node David Gibson
2019-12-17  4:41 ` [PULL 03/88] ppc/pnv: Drop "chip" link from POWER9 PSI object David Gibson
2019-12-17  4:41 ` [PULL 04/88] xive: Link "cpu" property to XiveTCTX::cs pointer David Gibson
2019-12-17  4:41 ` [PULL 05/88] xive: Link "xive" property to XiveSource::xive pointer David Gibson
2019-12-17  4:42 ` [PULL 06/88] xive: Link "xive" property to XiveEndSource::xrtr pointer David Gibson
2019-12-17  4:42 ` [PULL 07/88] ppc/pnv: Link "psi" property to PnvLpc::psi pointer David Gibson
2019-12-17  4:42 ` [PULL 08/88] ppc/pnv: Link "psi" property to PnvOCC::psi pointer David Gibson
2019-12-17  4:42 ` [PULL 09/88] ppc/pnv: Link "chip" property to PnvHomer::chip pointer David Gibson
2019-12-17  4:42 ` [PULL 10/88] ppc/pnv: Link "chip" property to PnvCore::chip pointer David Gibson
2019-12-17  4:42 ` [PULL 11/88] ppc/pnv: Link "chip" property to PnvXive::chip pointer David Gibson
2019-12-17  4:42 ` [PULL 12/88] xics: Link ICS_PROP_XICS property to ICSState::xics pointer David Gibson
2019-12-17  4:42 ` [PULL 13/88] xics: Link ICP_PROP_XICS property to ICPState::xics pointer David Gibson
2019-12-17  4:42 ` [PULL 14/88] xics: Link ICP_PROP_CPU property to ICPState::cs pointer David Gibson
2019-12-17  4:42 ` [PULL 15/88] spapr: Abort if XICS interrupt controller cannot be initialized David Gibson
2019-12-17  4:42 ` [PULL 16/88] ppc/pnv: Add a LPC "ranges" property David Gibson
2019-12-17  4:42 ` [PULL 17/88] ppc/xive: Record the IPB in the associated NVT David Gibson
2019-12-17  4:42 ` [PULL 18/88] ppc/xive: Introduce helpers for the NVT id David Gibson
2019-12-17  4:42 ` [PULL 19/88] ppc/pnv: Remove pnv_xive_vst_size() routine David Gibson
2019-12-17  4:42 ` [PULL 20/88] xive/kvm: Trigger interrupts from userspace David Gibson
2019-12-17  4:42 ` [PULL 21/88] ppc/pnv: Quiesce some XIVE errors David Gibson
2019-12-17  4:42 ` [PULL 22/88] ppc/xive: Introduce OS CAM line helpers David Gibson
2019-12-17  4:42 ` [PULL 23/88] ppc/xive: Check V bit in TM_PULL_POOL_CTX David Gibson
2019-12-17  4:42 ` [PULL 24/88] ipmi: Add support to customize OEM functions David Gibson
2019-12-17  4:42 ` [PULL 25/88] ppc/pnv: Add HIOMAP commands David Gibson
2019-12-17  4:42 ` [PULL 26/88] ppc/pnv: Create BMC devices at machine init David Gibson
2019-12-17  4:42 ` [PULL 27/88] ppc/xive: Introduce a XivePresenter interface David Gibson
2019-12-17  4:42 ` [PULL 28/88] ppc/xive: Implement the " David Gibson
2019-12-17  4:42 ` David Gibson [this message]
2019-12-17  4:42 ` [PULL 30/88] ppc/pnv: Loop on the threads of the chip to find a matching NVT David Gibson
2019-12-17  4:42 ` [PULL 31/88] ppc: Introduce a ppc_cpu_pir() helper David Gibson
2019-12-17  4:42 ` [PULL 32/88] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper David Gibson
2019-12-17  4:42 ` [PULL 33/88] ppc/pnv: Fix TIMA indirect access David Gibson
2019-12-17  4:42 ` [PULL 34/88] ppc/xive: Introduce a XiveFabric interface David Gibson
2019-12-17  4:42 ` [PULL 35/88] ppc/pnv: Implement the " David Gibson
2019-12-17  4:42 ` [PULL 36/88] ppc/spapr: " David Gibson
2019-12-17  4:42 ` [PULL 37/88] ppc/xive: Use the XiveFabric and XivePresenter interfaces David Gibson
2019-12-17  4:42 ` [PULL 38/88] ppc/xive: Extend the TIMA operation with a XivePresenter parameter David Gibson
2019-12-17  4:42 ` [PULL 39/88] linux-headers: Update David Gibson
2019-12-17  4:42 ` [PULL 40/88] spapr: Pass the maximum number of vCPUs to the KVM interrupt controller David Gibson
2019-12-17  4:42 ` [PULL 41/88] spapr/xics: Configure number of servers in KVM David Gibson
2019-12-17  4:42 ` [PULL 42/88] spapr/xive: " David Gibson
2019-12-17  4:42 ` [PULL 43/88] ppc/pnv: Clarify how the TIMA is accessed on a multichip system David Gibson
2019-12-17  4:42 ` [PULL 44/88] ppc/xive: Move the TIMA operations to the controller model David Gibson
2019-12-17  4:42 ` [PULL 45/88] ppc/xive: Remove the get_tctx() XiveRouter handler David Gibson
2019-12-17  4:42 ` [PULL 46/88] ppc/xive: Introduce a xive_tctx_ipb_update() helper David Gibson
2019-12-17  4:42 ` [PULL 47/88] ppc/xive: Synthesize interrupt from the saved IPB in the NVT David Gibson
2019-12-17  4:42 ` [PULL 48/88] ppc/pnv: Introduce a pnv_xive_block_id() helper David Gibson
2019-12-17  4:42 ` [PULL 49/88] ppc/pnv: Extend XiveRouter with a get_block_id() handler David Gibson
2019-12-17  4:42 ` [PULL 50/88] ppc/pnv: Dump the XIVE NVT table David Gibson
2019-12-17  4:42 ` [PULL 51/88] ppc: well form kvmppc_hint_smt_possible error hint helper David Gibson
2019-12-17  6:32   ` Markus Armbruster
2019-12-18  3:12     ` David Gibson
2019-12-17  4:42 ` [PULL 52/88] spapr: Don't trigger a CAS reboot for XICS/XIVE mode changeover David Gibson
2019-12-17  4:42 ` [PULL 53/88] spapr: Improve handling of fdt buffer size David Gibson
2019-12-17  4:42 ` [PULL 54/88] spapr: Fold h_cas_compose_response() into h_client_architecture_support() David Gibson
2019-12-17  4:42 ` [PULL 55/88] spapr: Simplify ovec diff David Gibson
2019-12-17  4:42 ` [PULL 56/88] ppc: Deassert the external interrupt pin in KVM on reset David Gibson
2019-12-17  4:42 ` [PULL 57/88] xics: Don't deassert outputs David Gibson
2019-12-17  4:42 ` [PULL 58/88] ppc: Don't use CPUPPCState::irq_input_state with modern Book3s CPU models David Gibson
2019-12-17  4:42 ` [PULL 59/88] ppc: Ignore the CPU_INTERRUPT_EXITTB interrupt with KVM David Gibson
2019-12-17  4:42 ` [PULL 60/88] ppc: Make PPCVirtualHypervisor an incomplete type David Gibson
2019-12-17  4:42 ` [PULL 61/88] target/ppc: Add POWER10 DD1.0 model information David Gibson
2019-12-17  4:42 ` [PULL 62/88] ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machine David Gibson
2019-12-17  4:42 ` [PULL 63/88] ppc/psi: cleanup definitions David Gibson
2019-12-17  4:42 ` [PULL 64/88] ppc/pnv: add a PSI bridge model for POWER10 David Gibson
2019-12-17  4:42 ` [PULL 65/88] ppc/pnv: add a LPC Controller " David Gibson
2019-12-17  4:43 ` [PULL 66/88] target/ppc: Implement the VTB for HV access David Gibson
2019-12-17  4:43 ` [PULL 67/88] target/ppc: Work [S]PURR implementation and add HV support David Gibson
2019-12-17  4:43 ` [PULL 68/88] target/ppc: Add SPR ASDR David Gibson
2019-12-17  4:43 ` [PULL 69/88] target/ppc: Add SPR TBU40 David Gibson
2019-12-17  4:43 ` [PULL 70/88] ppc/pnv: Loop on the whole hierarchy to populate the DT with the XSCOM nodes David Gibson
2019-12-17  4:43 ` [PULL 71/88] ppc/pnv: populate the DT with realized XSCOM devices David Gibson
2019-12-17  4:43 ` [PULL 72/88] ppc/pnv: Make PnvXScomInterface an incomplete type David Gibson
2019-12-17  4:43 ` [PULL 73/88] ppc/pnv: Introduce PBA registers David Gibson
2019-12-17  4:43 ` [PULL 74/88] ppc/pnv: Fix OCC common area region mapping David Gibson
2019-12-17  4:43 ` [PULL 75/88] ppc: Drop useless extern annotation for functions David Gibson
2019-12-17  4:43 ` [PULL 76/88] ppc/pnv: Introduce PnvPsiClass::compat David Gibson
2019-12-17  4:43 ` [PULL 77/88] ppc/pnv: Drop PnvPsiClass::chip_type David Gibson
2019-12-17  4:43 ` [PULL 78/88] ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compat David Gibson
2019-12-17  4:43 ` [PULL 79/88] ppc/pnv: Introduce PnvMachineClass::dt_power_mgt() David Gibson
2019-12-17  4:43 ` [PULL 80/88] ppc/pnv: Drop pnv_is_power9() and pnv_is_power10() helpers David Gibson
2019-12-17  4:43 ` [PULL 81/88] ppc/pnv: Introduce PnvChipClass::intc_print_info() method David Gibson
2019-12-17  4:43 ` [PULL 82/88] ppc/pnv: Introduce PnvChipClass::xscom_core_base() method David Gibson
2019-12-17  4:43 ` [PULL 83/88] ppc/pnv: Pass XSCOM base address and address size to pnv_dt_xscom() David Gibson
2019-12-17  4:43 ` [PULL 84/88] ppc/pnv: Pass content of the "compatible" property " David Gibson
2019-12-17  4:43 ` [PULL 85/88] ppc/pnv: Drop pnv_chip_is_power9() and pnv_chip_is_power10() helpers David Gibson
2019-12-17  4:43 ` [PULL 86/88] ppc/pnv: Introduce PnvChipClass::xscom_pcba() method David Gibson
2019-12-17  4:43 ` [PULL 87/88] ppc/pnv: Drop PnvChipClass::type David Gibson
2019-12-17  4:43 ` [PULL 88/88] pseries: Update SLOF firmware image David Gibson
2019-12-17 14:32 ` [PULL 00/88] ppc-for-5.0 queue 20191217 Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20191217044322.351838-30-david@gibson.dropbear.id.au \
    --to=david@gibson.dropbear.id.au \
    --cc=aik@ozlabs.ru \
    --cc=clg@kaod.org \
    --cc=groug@kaod.org \
    --cc=lvivier@redhat.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).