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From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org,
	groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org,
	David Gibson <david@gibson.dropbear.id.au>
Subject: [PULL 65/88] ppc/pnv: add a LPC Controller model for POWER10
Date: Tue, 17 Dec 2019 15:42:59 +1100	[thread overview]
Message-ID: <20191217044322.351838-66-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au>

From: Cédric Le Goater <clg@kaod.org>

Same a POWER9, only the MMIO window changes.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191205184454.10722-6-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 hw/ppc/pnv.c             | 25 ++++++++++++++++++++++---
 hw/ppc/pnv_lpc.c         | 30 ++++++++++++++++++++++--------
 include/hw/ppc/pnv.h     |  4 ++++
 include/hw/ppc/pnv_lpc.h |  6 +++++-
 4 files changed, 53 insertions(+), 12 deletions(-)

diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 09263ab747..67d0ad55b8 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -314,7 +314,7 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
         pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
     }
 
-    pnv_dt_lpc(chip, fdt, 0);
+    pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
 }
 
 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
@@ -332,6 +332,8 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
     if (chip->ram_size) {
         pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
     }
+
+    pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
 }
 
 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
@@ -601,8 +603,8 @@ static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
 
 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
 {
-    error_setg(errp, "No ISA bus!");
-    return NULL;
+    Pnv10Chip *chip10 = PNV10_CHIP(chip);
+    return pnv_lpc_isa_create(&chip10->lpc, false, errp);
 }
 
 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
@@ -1315,6 +1317,8 @@ static void pnv_chip_power10_instance_init(Object *obj)
 
     object_initialize_child(obj, "psi",  &chip10->psi, sizeof(chip10->psi),
                             TYPE_PNV10_PSI, &error_abort, NULL);
+    object_initialize_child(obj, "lpc",  &chip10->lpc, sizeof(chip10->lpc),
+                            TYPE_PNV10_LPC, &error_abort, NULL);
 }
 
 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
@@ -1349,6 +1353,21 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
     }
     pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
                             &PNV_PSI(&chip10->psi)->xscom_regs);
+
+    /* LPC */
+    object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi",
+                             &error_abort);
+    object_property_set_bool(OBJECT(&chip10->lpc), true, "realized",
+                             &local_err);
+    if (local_err) {
+        error_propagate(errp, local_err);
+        return;
+    }
+    memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
+                                &chip10->lpc.xscom_regs);
+
+    chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
+                                            (uint64_t) PNV10_LPCM_BASE(chip));
 }
 
 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index dd5374c838..18256d9ba3 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -122,26 +122,26 @@ static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
 }
 
 /* POWER9 only */
-int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset)
+int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset, uint64_t lpcm_addr,
+               uint64_t lpcm_size)
 {
     const char compat[] = "ibm,power9-lpcm-opb\0simple-bus";
     const char lpc_compat[] = "ibm,power9-lpc\0ibm,lpc";
     char *name;
     int offset, lpcm_offset;
-    uint64_t lpcm_addr = PNV9_LPCM_BASE(chip);
     uint32_t opb_ranges[8] = { 0,
                                cpu_to_be32(lpcm_addr >> 32),
                                cpu_to_be32((uint32_t)lpcm_addr),
-                               cpu_to_be32(PNV9_LPCM_SIZE / 2),
-                               cpu_to_be32(PNV9_LPCM_SIZE / 2),
+                               cpu_to_be32(lpcm_size / 2),
+                               cpu_to_be32(lpcm_size / 2),
                                cpu_to_be32(lpcm_addr >> 32),
-                               cpu_to_be32(PNV9_LPCM_SIZE / 2),
-                               cpu_to_be32(PNV9_LPCM_SIZE / 2),
+                               cpu_to_be32(lpcm_size / 2),
+                               cpu_to_be32(lpcm_size / 2),
     };
     uint32_t opb_reg[4] = { cpu_to_be32(lpcm_addr >> 32),
                             cpu_to_be32((uint32_t)lpcm_addr),
-                            cpu_to_be32(PNV9_LPCM_SIZE >> 32),
-                            cpu_to_be32((uint32_t)PNV9_LPCM_SIZE),
+                            cpu_to_be32(lpcm_size >> 32),
+                            cpu_to_be32((uint32_t)lpcm_size),
     };
     uint32_t lpc_ranges[12] = { 0, 0,
                                 cpu_to_be32(LPC_MEM_OPB_ADDR),
@@ -691,6 +691,19 @@ static const TypeInfo pnv_lpc_power9_info = {
     .class_init    = pnv_lpc_power9_class_init,
 };
 
+static void pnv_lpc_power10_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "PowerNV LPC Controller POWER10";
+}
+
+static const TypeInfo pnv_lpc_power10_info = {
+    .name          = TYPE_PNV10_LPC,
+    .parent        = TYPE_PNV9_LPC,
+    .class_init    = pnv_lpc_power10_class_init,
+};
+
 static void pnv_lpc_realize(DeviceState *dev, Error **errp)
 {
     PnvLpcController *lpc = PNV_LPC(dev);
@@ -764,6 +777,7 @@ static void pnv_lpc_register_types(void)
     type_register_static(&pnv_lpc_info);
     type_register_static(&pnv_lpc_power8_info);
     type_register_static(&pnv_lpc_power9_info);
+    type_register_static(&pnv_lpc_power10_info);
 }
 
 type_init(pnv_lpc_register_types)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 47b7370b27..56d1161515 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -115,6 +115,7 @@ typedef struct Pnv10Chip {
 
     /*< public >*/
     Pnv9Psi      psi;
+    PnvLpcController lpc;
 } Pnv10Chip;
 
 typedef struct PnvChipClass {
@@ -329,6 +330,9 @@ IPMIBmc *pnv_bmc_create(void);
 #define PNV10_XSCOM_SIZE             0x0000000400000000ull
 #define PNV10_XSCOM_BASE(chip)       PNV10_CHIP_BASE(chip, 0x00603fc00000000ull)
 
+#define PNV10_LPCM_SIZE             0x0000000100000000ull
+#define PNV10_LPCM_BASE(chip)       PNV10_CHIP_BASE(chip, 0x0006030000000000ull)
+
 #define PNV10_PSIHB_ESB_SIZE        0x0000000000100000ull
 #define PNV10_PSIHB_ESB_BASE(chip)  PNV10_CHIP_BASE(chip, 0x0006030202000000ull)
 
diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h
index f659410716..c1ec85d5e2 100644
--- a/include/hw/ppc/pnv_lpc.h
+++ b/include/hw/ppc/pnv_lpc.h
@@ -31,6 +31,9 @@
 #define TYPE_PNV9_LPC TYPE_PNV_LPC "-POWER9"
 #define PNV9_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV9_LPC)
 
+#define TYPE_PNV10_LPC TYPE_PNV_LPC "-POWER10"
+#define PNV10_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV10_LPC)
+
 typedef struct PnvLpcController {
     DeviceState parent;
 
@@ -97,6 +100,7 @@ typedef struct PnvLpcClass {
 struct PnvChip;
 
 ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp);
-int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset);
+int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset,
+               uint64_t lpcm_addr, uint64_t lpcm_size);
 
 #endif /* PPC_PNV_LPC_H */
-- 
2.23.0



  parent reply	other threads:[~2019-12-17  5:26 UTC|newest]

Thread overview: 94+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-17  4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
2019-12-17  4:41 ` [PULL 01/88] ppc/pnv: Add a PNOR model David Gibson
2020-01-07 14:43   ` Peter Maydell
2020-01-07 16:26     ` Cédric Le Goater
2019-12-17  4:41 ` [PULL 02/88] ppc/pnv: Add a "/qemu" device tree node David Gibson
2019-12-17  4:41 ` [PULL 03/88] ppc/pnv: Drop "chip" link from POWER9 PSI object David Gibson
2019-12-17  4:41 ` [PULL 04/88] xive: Link "cpu" property to XiveTCTX::cs pointer David Gibson
2019-12-17  4:41 ` [PULL 05/88] xive: Link "xive" property to XiveSource::xive pointer David Gibson
2019-12-17  4:42 ` [PULL 06/88] xive: Link "xive" property to XiveEndSource::xrtr pointer David Gibson
2019-12-17  4:42 ` [PULL 07/88] ppc/pnv: Link "psi" property to PnvLpc::psi pointer David Gibson
2019-12-17  4:42 ` [PULL 08/88] ppc/pnv: Link "psi" property to PnvOCC::psi pointer David Gibson
2019-12-17  4:42 ` [PULL 09/88] ppc/pnv: Link "chip" property to PnvHomer::chip pointer David Gibson
2019-12-17  4:42 ` [PULL 10/88] ppc/pnv: Link "chip" property to PnvCore::chip pointer David Gibson
2019-12-17  4:42 ` [PULL 11/88] ppc/pnv: Link "chip" property to PnvXive::chip pointer David Gibson
2019-12-17  4:42 ` [PULL 12/88] xics: Link ICS_PROP_XICS property to ICSState::xics pointer David Gibson
2019-12-17  4:42 ` [PULL 13/88] xics: Link ICP_PROP_XICS property to ICPState::xics pointer David Gibson
2019-12-17  4:42 ` [PULL 14/88] xics: Link ICP_PROP_CPU property to ICPState::cs pointer David Gibson
2019-12-17  4:42 ` [PULL 15/88] spapr: Abort if XICS interrupt controller cannot be initialized David Gibson
2019-12-17  4:42 ` [PULL 16/88] ppc/pnv: Add a LPC "ranges" property David Gibson
2019-12-17  4:42 ` [PULL 17/88] ppc/xive: Record the IPB in the associated NVT David Gibson
2019-12-17  4:42 ` [PULL 18/88] ppc/xive: Introduce helpers for the NVT id David Gibson
2019-12-17  4:42 ` [PULL 19/88] ppc/pnv: Remove pnv_xive_vst_size() routine David Gibson
2019-12-17  4:42 ` [PULL 20/88] xive/kvm: Trigger interrupts from userspace David Gibson
2019-12-17  4:42 ` [PULL 21/88] ppc/pnv: Quiesce some XIVE errors David Gibson
2019-12-17  4:42 ` [PULL 22/88] ppc/xive: Introduce OS CAM line helpers David Gibson
2019-12-17  4:42 ` [PULL 23/88] ppc/xive: Check V bit in TM_PULL_POOL_CTX David Gibson
2019-12-17  4:42 ` [PULL 24/88] ipmi: Add support to customize OEM functions David Gibson
2019-12-17  4:42 ` [PULL 25/88] ppc/pnv: Add HIOMAP commands David Gibson
2019-12-17  4:42 ` [PULL 26/88] ppc/pnv: Create BMC devices at machine init David Gibson
2019-12-17  4:42 ` [PULL 27/88] ppc/xive: Introduce a XivePresenter interface David Gibson
2019-12-17  4:42 ` [PULL 28/88] ppc/xive: Implement the " David Gibson
2019-12-17  4:42 ` [PULL 29/88] ppc/pnv: Instantiate cores separately David Gibson
2019-12-17  4:42 ` [PULL 30/88] ppc/pnv: Loop on the threads of the chip to find a matching NVT David Gibson
2019-12-17  4:42 ` [PULL 31/88] ppc: Introduce a ppc_cpu_pir() helper David Gibson
2019-12-17  4:42 ` [PULL 32/88] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper David Gibson
2019-12-17  4:42 ` [PULL 33/88] ppc/pnv: Fix TIMA indirect access David Gibson
2019-12-17  4:42 ` [PULL 34/88] ppc/xive: Introduce a XiveFabric interface David Gibson
2019-12-17  4:42 ` [PULL 35/88] ppc/pnv: Implement the " David Gibson
2019-12-17  4:42 ` [PULL 36/88] ppc/spapr: " David Gibson
2019-12-17  4:42 ` [PULL 37/88] ppc/xive: Use the XiveFabric and XivePresenter interfaces David Gibson
2019-12-17  4:42 ` [PULL 38/88] ppc/xive: Extend the TIMA operation with a XivePresenter parameter David Gibson
2019-12-17  4:42 ` [PULL 39/88] linux-headers: Update David Gibson
2019-12-17  4:42 ` [PULL 40/88] spapr: Pass the maximum number of vCPUs to the KVM interrupt controller David Gibson
2019-12-17  4:42 ` [PULL 41/88] spapr/xics: Configure number of servers in KVM David Gibson
2019-12-17  4:42 ` [PULL 42/88] spapr/xive: " David Gibson
2019-12-17  4:42 ` [PULL 43/88] ppc/pnv: Clarify how the TIMA is accessed on a multichip system David Gibson
2019-12-17  4:42 ` [PULL 44/88] ppc/xive: Move the TIMA operations to the controller model David Gibson
2019-12-17  4:42 ` [PULL 45/88] ppc/xive: Remove the get_tctx() XiveRouter handler David Gibson
2019-12-17  4:42 ` [PULL 46/88] ppc/xive: Introduce a xive_tctx_ipb_update() helper David Gibson
2019-12-17  4:42 ` [PULL 47/88] ppc/xive: Synthesize interrupt from the saved IPB in the NVT David Gibson
2019-12-17  4:42 ` [PULL 48/88] ppc/pnv: Introduce a pnv_xive_block_id() helper David Gibson
2019-12-17  4:42 ` [PULL 49/88] ppc/pnv: Extend XiveRouter with a get_block_id() handler David Gibson
2019-12-17  4:42 ` [PULL 50/88] ppc/pnv: Dump the XIVE NVT table David Gibson
2019-12-17  4:42 ` [PULL 51/88] ppc: well form kvmppc_hint_smt_possible error hint helper David Gibson
2019-12-17  6:32   ` Markus Armbruster
2019-12-18  3:12     ` David Gibson
2019-12-17  4:42 ` [PULL 52/88] spapr: Don't trigger a CAS reboot for XICS/XIVE mode changeover David Gibson
2019-12-17  4:42 ` [PULL 53/88] spapr: Improve handling of fdt buffer size David Gibson
2019-12-17  4:42 ` [PULL 54/88] spapr: Fold h_cas_compose_response() into h_client_architecture_support() David Gibson
2019-12-17  4:42 ` [PULL 55/88] spapr: Simplify ovec diff David Gibson
2019-12-17  4:42 ` [PULL 56/88] ppc: Deassert the external interrupt pin in KVM on reset David Gibson
2019-12-17  4:42 ` [PULL 57/88] xics: Don't deassert outputs David Gibson
2019-12-17  4:42 ` [PULL 58/88] ppc: Don't use CPUPPCState::irq_input_state with modern Book3s CPU models David Gibson
2019-12-17  4:42 ` [PULL 59/88] ppc: Ignore the CPU_INTERRUPT_EXITTB interrupt with KVM David Gibson
2019-12-17  4:42 ` [PULL 60/88] ppc: Make PPCVirtualHypervisor an incomplete type David Gibson
2019-12-17  4:42 ` [PULL 61/88] target/ppc: Add POWER10 DD1.0 model information David Gibson
2019-12-17  4:42 ` [PULL 62/88] ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machine David Gibson
2019-12-17  4:42 ` [PULL 63/88] ppc/psi: cleanup definitions David Gibson
2019-12-17  4:42 ` [PULL 64/88] ppc/pnv: add a PSI bridge model for POWER10 David Gibson
2019-12-17  4:42 ` David Gibson [this message]
2019-12-17  4:43 ` [PULL 66/88] target/ppc: Implement the VTB for HV access David Gibson
2019-12-17  4:43 ` [PULL 67/88] target/ppc: Work [S]PURR implementation and add HV support David Gibson
2019-12-17  4:43 ` [PULL 68/88] target/ppc: Add SPR ASDR David Gibson
2019-12-17  4:43 ` [PULL 69/88] target/ppc: Add SPR TBU40 David Gibson
2019-12-17  4:43 ` [PULL 70/88] ppc/pnv: Loop on the whole hierarchy to populate the DT with the XSCOM nodes David Gibson
2019-12-17  4:43 ` [PULL 71/88] ppc/pnv: populate the DT with realized XSCOM devices David Gibson
2019-12-17  4:43 ` [PULL 72/88] ppc/pnv: Make PnvXScomInterface an incomplete type David Gibson
2019-12-17  4:43 ` [PULL 73/88] ppc/pnv: Introduce PBA registers David Gibson
2019-12-17  4:43 ` [PULL 74/88] ppc/pnv: Fix OCC common area region mapping David Gibson
2019-12-17  4:43 ` [PULL 75/88] ppc: Drop useless extern annotation for functions David Gibson
2019-12-17  4:43 ` [PULL 76/88] ppc/pnv: Introduce PnvPsiClass::compat David Gibson
2019-12-17  4:43 ` [PULL 77/88] ppc/pnv: Drop PnvPsiClass::chip_type David Gibson
2019-12-17  4:43 ` [PULL 78/88] ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compat David Gibson
2019-12-17  4:43 ` [PULL 79/88] ppc/pnv: Introduce PnvMachineClass::dt_power_mgt() David Gibson
2019-12-17  4:43 ` [PULL 80/88] ppc/pnv: Drop pnv_is_power9() and pnv_is_power10() helpers David Gibson
2019-12-17  4:43 ` [PULL 81/88] ppc/pnv: Introduce PnvChipClass::intc_print_info() method David Gibson
2019-12-17  4:43 ` [PULL 82/88] ppc/pnv: Introduce PnvChipClass::xscom_core_base() method David Gibson
2019-12-17  4:43 ` [PULL 83/88] ppc/pnv: Pass XSCOM base address and address size to pnv_dt_xscom() David Gibson
2019-12-17  4:43 ` [PULL 84/88] ppc/pnv: Pass content of the "compatible" property " David Gibson
2019-12-17  4:43 ` [PULL 85/88] ppc/pnv: Drop pnv_chip_is_power9() and pnv_chip_is_power10() helpers David Gibson
2019-12-17  4:43 ` [PULL 86/88] ppc/pnv: Introduce PnvChipClass::xscom_pcba() method David Gibson
2019-12-17  4:43 ` [PULL 87/88] ppc/pnv: Drop PnvChipClass::type David Gibson
2019-12-17  4:43 ` [PULL 88/88] pseries: Update SLOF firmware image David Gibson
2019-12-17 14:32 ` [PULL 00/88] ppc-for-5.0 queue 20191217 Peter Maydell

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