From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org,
	groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org,
	David Gibson <david@gibson.dropbear.id.au>
Subject: [PULL 78/88] ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compat
Date: Tue, 17 Dec 2019 15:43:12 +1100	[thread overview]
Message-ID: <20191217044322.351838-79-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au>
From: Greg Kurz <groug@kaod.org>
The pnv_dt_create() function generates different contents for the
"compatible" property of the root node in the DT, depending on the
CPU type. This is open coded with multiple ifs using pnv_is_powerXX()
helpers.
It seems cleaner to achieve with QOM. Introduce a base class for the
powernv machine and a compat attribute that each child class can use
to provide the value for the "compatible" property.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157623839085.360005.4046508784077843216.stgit@bahia.lan>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[dwg: Folded in small fix Greg spotted after posting]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 hw/ppc/pnv.c         | 32 ++++++++++++++++++--------------
 include/hw/ppc/pnv.h | 13 +++++++++++++
 2 files changed, 31 insertions(+), 14 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 0be0b6b411..97845e7bde 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -484,9 +484,7 @@ static void pnv_dt_power_mgt(void *fdt)
 
 static void *pnv_dt_create(MachineState *machine)
 {
-    const char plat_compat8[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
-    const char plat_compat9[] = "qemu,powernv9\0ibm,powernv";
-    const char plat_compat10[] = "qemu,powernv10\0ibm,powernv";
+    PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
     PnvMachineState *pnv = PNV_MACHINE(machine);
     void *fdt;
     char *buf;
@@ -504,17 +502,7 @@ static void *pnv_dt_create(MachineState *machine)
     _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
     _FDT((fdt_setprop_string(fdt, 0, "model",
                              "IBM PowerNV (emulated by qemu)")));
-    if (pnv_is_power10(pnv)) {
-        _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat10,
-                          sizeof(plat_compat10))));
-    } else if (pnv_is_power9(pnv)) {
-        _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat9,
-                          sizeof(plat_compat9))));
-    } else {
-        _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat8,
-                          sizeof(plat_compat8))));
-    }
-
+    _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size)));
 
     buf =  qemu_uuid_unparse_strdup(&qemu_uuid);
     _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
@@ -1692,6 +1680,8 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
     XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
+    PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
+    static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
 
     mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
@@ -1699,26 +1689,39 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
     xic->icp_get = pnv_icp_get;
     xic->ics_get = pnv_ics_get;
     xic->ics_resend = pnv_ics_resend;
+
+    pmc->compat = compat;
+    pmc->compat_size = sizeof(compat);
 }
 
 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
     XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
+    PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
+    static const char compat[] = "qemu,powernv9\0ibm,powernv";
 
     mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
     xfc->match_nvt = pnv_match_nvt;
 
     mc->alias = "powernv";
+
+    pmc->compat = compat;
+    pmc->compat_size = sizeof(compat);
 }
 
 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
+    PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
+    static const char compat[] = "qemu,powernv10\0ibm,powernv";
 
     mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0");
+
+    pmc->compat = compat;
+    pmc->compat_size = sizeof(compat);
 }
 
 static void pnv_machine_class_init(ObjectClass *oc, void *data)
@@ -1796,6 +1799,7 @@ static const TypeInfo types[] = {
         .instance_size = sizeof(PnvMachineState),
         .instance_init = pnv_machine_instance_init,
         .class_init    = pnv_machine_class_init,
+        .class_size    = sizeof(PnvMachineClass),
         .interfaces = (InterfaceInfo[]) {
             { TYPE_INTERRUPT_STATS_PROVIDER },
             { },
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 92f80b1cce..d534746bd4 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -185,6 +185,19 @@ PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
 #define TYPE_PNV_MACHINE       MACHINE_TYPE_NAME("powernv")
 #define PNV_MACHINE(obj) \
     OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE)
+#define PNV_MACHINE_GET_CLASS(obj) \
+    OBJECT_GET_CLASS(PnvMachineClass, obj, TYPE_PNV_MACHINE)
+#define PNV_MACHINE_CLASS(klass) \
+    OBJECT_CLASS_CHECK(PnvMachineClass, klass, TYPE_PNV_MACHINE)
+
+typedef struct PnvMachineClass {
+    /*< private >*/
+    MachineClass parent_class;
+
+    /*< public >*/
+    const char *compat;
+    int compat_size;
+} PnvMachineClass;
 
 typedef struct PnvMachineState {
     /*< private >*/
-- 
2.23.0
next prev parent reply	other threads:[~2019-12-17  5:53 UTC|newest]
Thread overview: 94+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-17  4:41 [PULL 00/88] ppc-for-5.0 queue 20191217 David Gibson
2019-12-17  4:41 ` [PULL 01/88] ppc/pnv: Add a PNOR model David Gibson
2020-01-07 14:43   ` Peter Maydell
2020-01-07 16:26     ` Cédric Le Goater
2019-12-17  4:41 ` [PULL 02/88] ppc/pnv: Add a "/qemu" device tree node David Gibson
2019-12-17  4:41 ` [PULL 03/88] ppc/pnv: Drop "chip" link from POWER9 PSI object David Gibson
2019-12-17  4:41 ` [PULL 04/88] xive: Link "cpu" property to XiveTCTX::cs pointer David Gibson
2019-12-17  4:41 ` [PULL 05/88] xive: Link "xive" property to XiveSource::xive pointer David Gibson
2019-12-17  4:42 ` [PULL 06/88] xive: Link "xive" property to XiveEndSource::xrtr pointer David Gibson
2019-12-17  4:42 ` [PULL 07/88] ppc/pnv: Link "psi" property to PnvLpc::psi pointer David Gibson
2019-12-17  4:42 ` [PULL 08/88] ppc/pnv: Link "psi" property to PnvOCC::psi pointer David Gibson
2019-12-17  4:42 ` [PULL 09/88] ppc/pnv: Link "chip" property to PnvHomer::chip pointer David Gibson
2019-12-17  4:42 ` [PULL 10/88] ppc/pnv: Link "chip" property to PnvCore::chip pointer David Gibson
2019-12-17  4:42 ` [PULL 11/88] ppc/pnv: Link "chip" property to PnvXive::chip pointer David Gibson
2019-12-17  4:42 ` [PULL 12/88] xics: Link ICS_PROP_XICS property to ICSState::xics pointer David Gibson
2019-12-17  4:42 ` [PULL 13/88] xics: Link ICP_PROP_XICS property to ICPState::xics pointer David Gibson
2019-12-17  4:42 ` [PULL 14/88] xics: Link ICP_PROP_CPU property to ICPState::cs pointer David Gibson
2019-12-17  4:42 ` [PULL 15/88] spapr: Abort if XICS interrupt controller cannot be initialized David Gibson
2019-12-17  4:42 ` [PULL 16/88] ppc/pnv: Add a LPC "ranges" property David Gibson
2019-12-17  4:42 ` [PULL 17/88] ppc/xive: Record the IPB in the associated NVT David Gibson
2019-12-17  4:42 ` [PULL 18/88] ppc/xive: Introduce helpers for the NVT id David Gibson
2019-12-17  4:42 ` [PULL 19/88] ppc/pnv: Remove pnv_xive_vst_size() routine David Gibson
2019-12-17  4:42 ` [PULL 20/88] xive/kvm: Trigger interrupts from userspace David Gibson
2019-12-17  4:42 ` [PULL 21/88] ppc/pnv: Quiesce some XIVE errors David Gibson
2019-12-17  4:42 ` [PULL 22/88] ppc/xive: Introduce OS CAM line helpers David Gibson
2019-12-17  4:42 ` [PULL 23/88] ppc/xive: Check V bit in TM_PULL_POOL_CTX David Gibson
2019-12-17  4:42 ` [PULL 24/88] ipmi: Add support to customize OEM functions David Gibson
2019-12-17  4:42 ` [PULL 25/88] ppc/pnv: Add HIOMAP commands David Gibson
2019-12-17  4:42 ` [PULL 26/88] ppc/pnv: Create BMC devices at machine init David Gibson
2019-12-17  4:42 ` [PULL 27/88] ppc/xive: Introduce a XivePresenter interface David Gibson
2019-12-17  4:42 ` [PULL 28/88] ppc/xive: Implement the " David Gibson
2019-12-17  4:42 ` [PULL 29/88] ppc/pnv: Instantiate cores separately David Gibson
2019-12-17  4:42 ` [PULL 30/88] ppc/pnv: Loop on the threads of the chip to find a matching NVT David Gibson
2019-12-17  4:42 ` [PULL 31/88] ppc: Introduce a ppc_cpu_pir() helper David Gibson
2019-12-17  4:42 ` [PULL 32/88] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper David Gibson
2019-12-17  4:42 ` [PULL 33/88] ppc/pnv: Fix TIMA indirect access David Gibson
2019-12-17  4:42 ` [PULL 34/88] ppc/xive: Introduce a XiveFabric interface David Gibson
2019-12-17  4:42 ` [PULL 35/88] ppc/pnv: Implement the " David Gibson
2019-12-17  4:42 ` [PULL 36/88] ppc/spapr: " David Gibson
2019-12-17  4:42 ` [PULL 37/88] ppc/xive: Use the XiveFabric and XivePresenter interfaces David Gibson
2019-12-17  4:42 ` [PULL 38/88] ppc/xive: Extend the TIMA operation with a XivePresenter parameter David Gibson
2019-12-17  4:42 ` [PULL 39/88] linux-headers: Update David Gibson
2019-12-17  4:42 ` [PULL 40/88] spapr: Pass the maximum number of vCPUs to the KVM interrupt controller David Gibson
2019-12-17  4:42 ` [PULL 41/88] spapr/xics: Configure number of servers in KVM David Gibson
2019-12-17  4:42 ` [PULL 42/88] spapr/xive: " David Gibson
2019-12-17  4:42 ` [PULL 43/88] ppc/pnv: Clarify how the TIMA is accessed on a multichip system David Gibson
2019-12-17  4:42 ` [PULL 44/88] ppc/xive: Move the TIMA operations to the controller model David Gibson
2019-12-17  4:42 ` [PULL 45/88] ppc/xive: Remove the get_tctx() XiveRouter handler David Gibson
2019-12-17  4:42 ` [PULL 46/88] ppc/xive: Introduce a xive_tctx_ipb_update() helper David Gibson
2019-12-17  4:42 ` [PULL 47/88] ppc/xive: Synthesize interrupt from the saved IPB in the NVT David Gibson
2019-12-17  4:42 ` [PULL 48/88] ppc/pnv: Introduce a pnv_xive_block_id() helper David Gibson
2019-12-17  4:42 ` [PULL 49/88] ppc/pnv: Extend XiveRouter with a get_block_id() handler David Gibson
2019-12-17  4:42 ` [PULL 50/88] ppc/pnv: Dump the XIVE NVT table David Gibson
2019-12-17  4:42 ` [PULL 51/88] ppc: well form kvmppc_hint_smt_possible error hint helper David Gibson
2019-12-17  6:32   ` Markus Armbruster
2019-12-18  3:12     ` David Gibson
2019-12-17  4:42 ` [PULL 52/88] spapr: Don't trigger a CAS reboot for XICS/XIVE mode changeover David Gibson
2019-12-17  4:42 ` [PULL 53/88] spapr: Improve handling of fdt buffer size David Gibson
2019-12-17  4:42 ` [PULL 54/88] spapr: Fold h_cas_compose_response() into h_client_architecture_support() David Gibson
2019-12-17  4:42 ` [PULL 55/88] spapr: Simplify ovec diff David Gibson
2019-12-17  4:42 ` [PULL 56/88] ppc: Deassert the external interrupt pin in KVM on reset David Gibson
2019-12-17  4:42 ` [PULL 57/88] xics: Don't deassert outputs David Gibson
2019-12-17  4:42 ` [PULL 58/88] ppc: Don't use CPUPPCState::irq_input_state with modern Book3s CPU models David Gibson
2019-12-17  4:42 ` [PULL 59/88] ppc: Ignore the CPU_INTERRUPT_EXITTB interrupt with KVM David Gibson
2019-12-17  4:42 ` [PULL 60/88] ppc: Make PPCVirtualHypervisor an incomplete type David Gibson
2019-12-17  4:42 ` [PULL 61/88] target/ppc: Add POWER10 DD1.0 model information David Gibson
2019-12-17  4:42 ` [PULL 62/88] ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machine David Gibson
2019-12-17  4:42 ` [PULL 63/88] ppc/psi: cleanup definitions David Gibson
2019-12-17  4:42 ` [PULL 64/88] ppc/pnv: add a PSI bridge model for POWER10 David Gibson
2019-12-17  4:42 ` [PULL 65/88] ppc/pnv: add a LPC Controller " David Gibson
2019-12-17  4:43 ` [PULL 66/88] target/ppc: Implement the VTB for HV access David Gibson
2019-12-17  4:43 ` [PULL 67/88] target/ppc: Work [S]PURR implementation and add HV support David Gibson
2019-12-17  4:43 ` [PULL 68/88] target/ppc: Add SPR ASDR David Gibson
2019-12-17  4:43 ` [PULL 69/88] target/ppc: Add SPR TBU40 David Gibson
2019-12-17  4:43 ` [PULL 70/88] ppc/pnv: Loop on the whole hierarchy to populate the DT with the XSCOM nodes David Gibson
2019-12-17  4:43 ` [PULL 71/88] ppc/pnv: populate the DT with realized XSCOM devices David Gibson
2019-12-17  4:43 ` [PULL 72/88] ppc/pnv: Make PnvXScomInterface an incomplete type David Gibson
2019-12-17  4:43 ` [PULL 73/88] ppc/pnv: Introduce PBA registers David Gibson
2019-12-17  4:43 ` [PULL 74/88] ppc/pnv: Fix OCC common area region mapping David Gibson
2019-12-17  4:43 ` [PULL 75/88] ppc: Drop useless extern annotation for functions David Gibson
2019-12-17  4:43 ` [PULL 76/88] ppc/pnv: Introduce PnvPsiClass::compat David Gibson
2019-12-17  4:43 ` [PULL 77/88] ppc/pnv: Drop PnvPsiClass::chip_type David Gibson
2019-12-17  4:43 ` David Gibson [this message]
2019-12-17  4:43 ` [PULL 79/88] ppc/pnv: Introduce PnvMachineClass::dt_power_mgt() David Gibson
2019-12-17  4:43 ` [PULL 80/88] ppc/pnv: Drop pnv_is_power9() and pnv_is_power10() helpers David Gibson
2019-12-17  4:43 ` [PULL 81/88] ppc/pnv: Introduce PnvChipClass::intc_print_info() method David Gibson
2019-12-17  4:43 ` [PULL 82/88] ppc/pnv: Introduce PnvChipClass::xscom_core_base() method David Gibson
2019-12-17  4:43 ` [PULL 83/88] ppc/pnv: Pass XSCOM base address and address size to pnv_dt_xscom() David Gibson
2019-12-17  4:43 ` [PULL 84/88] ppc/pnv: Pass content of the "compatible" property " David Gibson
2019-12-17  4:43 ` [PULL 85/88] ppc/pnv: Drop pnv_chip_is_power9() and pnv_chip_is_power10() helpers David Gibson
2019-12-17  4:43 ` [PULL 86/88] ppc/pnv: Introduce PnvChipClass::xscom_pcba() method David Gibson
2019-12-17  4:43 ` [PULL 87/88] ppc/pnv: Drop PnvChipClass::type David Gibson
2019-12-17  4:43 ` [PULL 88/88] pseries: Update SLOF firmware image David Gibson
2019-12-17 14:32 ` [PULL 00/88] ppc-for-5.0 queue 20191217 Peter Maydell
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