From: Michael Rolnik <mrolnik@gmail.com>
To: qemu-devel@nongnu.org
Cc: thuth@redhat.com, Michael Rolnik <mrolnik@gmail.com>,
me@xcancerberox.com.ar, richard.henderson@linaro.org,
dovgaluk@ispras.ru, imammedo@redhat.com, philmd@redhat.com,
aleksandar.m.mail@gmail.com
Subject: [PATCH v39 09/22] target/avr: Add instruction translation - MCU Control Instructions
Date: Wed, 18 Dec 2019 23:03:16 +0200 [thread overview]
Message-ID: <20191218210329.1960-10-mrolnik@gmail.com> (raw)
In-Reply-To: <20191218210329.1960-1-mrolnik@gmail.com>
This includes:
- BREAK
- NOP
- SLEEP
- WDR
Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
---
target/avr/translate.c | 68 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index e303a1f4cc..46cbcc9305 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -2606,3 +2606,71 @@ static bool trans_BCLR(DisasContext *ctx, arg_BCLR *a)
return true;
}
+
+/*
+ * MCU Control Instructions
+ */
+
+/*
+ * The BREAK instruction is used by the On-chip Debug system, and is
+ * normally not used in the application software. When the BREAK instruction is
+ * executed, the AVR CPU is set in the Stopped Mode. This gives the On-chip
+ * Debugger access to internal resources. If any Lock bits are set, or either
+ * the JTAGEN or OCDEN Fuses are unprogrammed, the CPU will treat the BREAK
+ * instruction as a NOP and will not enter the Stopped mode. This instruction
+ * is not available in all devices. Refer to the device specific instruction
+ * set summary.
+ */
+static bool trans_BREAK(DisasContext *ctx, arg_BREAK *a)
+{
+ if (!avr_have_feature(ctx, AVR_FEATURE_BREAK)) {
+ return true;
+ }
+
+#ifdef BREAKPOINT_ON_BREAK
+ tcg_gen_movi_tl(cpu_pc, ctx->npc - 1);
+ gen_helper_debug(cpu_env);
+ ctx->bstate = DISAS_EXIT;
+#else
+ /* NOP */
+#endif
+
+ return true;
+}
+
+
+/*
+ * This instruction performs a single cycle No Operation.
+ */
+static bool trans_NOP(DisasContext *ctx, arg_NOP *a)
+{
+
+ /* NOP */
+
+ return true;
+}
+
+
+/*
+ * This instruction sets the circuit in sleep mode defined by the MCU
+ * Control Register.
+ */
+static bool trans_SLEEP(DisasContext *ctx, arg_SLEEP *a)
+{
+ gen_helper_sleep(cpu_env);
+ ctx->bstate = DISAS_NORETURN;
+ return true;
+}
+
+
+/*
+ * This instruction resets the Watchdog Timer. This instruction must be
+ * executed within a limited time given by the WD prescaler. See the Watchdog
+ * Timer hardware specification.
+ */
+static bool trans_WDR(DisasContext *ctx, arg_WDR *a)
+{
+ gen_helper_wdr(cpu_env);
+
+ return true;
+}
--
2.17.2 (Apple Git-113)
next prev parent reply other threads:[~2019-12-18 21:06 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-18 21:03 [PATCH v39 00/22] QEMU AVR 8 bit cores Michael Rolnik
2019-12-18 21:03 ` [PATCH v39 01/22] target/avr: Add outward facing interfaces and core CPU logic Michael Rolnik
2019-12-21 10:53 ` Aleksandar Markovic
2019-12-21 11:22 ` Philippe Mathieu-Daudé
2019-12-21 12:32 ` Aleksandar Markovic
2019-12-18 21:03 ` [PATCH v39 02/22] target/avr: Add instruction helpers Michael Rolnik
2019-12-18 21:03 ` [PATCH v39 03/22] target/avr: Add instruction decoding Michael Rolnik
2019-12-21 11:18 ` Aleksandar Markovic
2019-12-21 15:57 ` Michael Rolnik
2019-12-21 16:21 ` Aleksandar Markovic
2019-12-21 17:15 ` Aleksandar Markovic
2019-12-28 19:31 ` Michael Rolnik
2019-12-29 14:37 ` Aleksandar Markovic
2019-12-18 21:03 ` [PATCH v39 04/22] target/avr: Add instruction translation - Registers definition Michael Rolnik
2019-12-22 15:54 ` Aleksandar Markovic
2019-12-18 21:03 ` [PATCH v39 05/22] target/avr: Add instruction translation - Arithmetic and Logic Instructions Michael Rolnik
2019-12-22 15:41 ` Aleksandar Markovic
2019-12-18 21:03 ` [PATCH v39 06/22] target/avr: Add instruction translation - Branch Instructions Michael Rolnik
2019-12-18 21:03 ` [PATCH v39 07/22] target/avr: Add instruction translation - Data Transfer Instructions Michael Rolnik
2019-12-18 21:03 ` [PATCH v39 08/22] target/avr: Add instruction translation - Bit and Bit-test Instructions Michael Rolnik
2019-12-18 21:03 ` Michael Rolnik [this message]
2019-12-18 21:03 ` [PATCH v39 10/22] target/avr: Add instruction translation - CPU main translation function Michael Rolnik
2019-12-18 21:03 ` [PATCH v39 11/22] target/avr: Add instruction disassembly function Michael Rolnik
2019-12-18 21:03 ` [PATCH v39 12/22] target/avr: Add limited support for USART peripheral Michael Rolnik
2019-12-20 15:56 ` Philippe Mathieu-Daudé
2019-12-18 21:03 ` [PATCH v39 13/22] target/avr: Add limited support for 16 bit timer peripheral Michael Rolnik
2019-12-18 21:03 ` [PATCH v39 14/22] target/avr: Add dummy mask device Michael Rolnik
2019-12-23 8:46 ` Aleksandar Markovic
2019-12-28 18:52 ` Michael Rolnik
2019-12-18 21:03 ` [PATCH v39 15/22] target/avr: Add example board configuration Michael Rolnik
2019-12-20 9:51 ` Igor Mammedov
2019-12-20 12:30 ` Michael Rolnik
2019-12-20 15:18 ` Igor Mammedov
2019-12-20 23:12 ` Philippe Mathieu-Daudé
2020-01-21 21:32 ` Philippe Mathieu-Daudé
2019-12-18 21:03 ` [PATCH v39 16/22] target/avr: Add section about AVR into QEMU documentation Michael Rolnik
2019-12-18 21:03 ` [PATCH v39 17/22] target/avr: Register AVR support with the rest of QEMU Michael Rolnik
2019-12-18 21:03 ` [PATCH v39 18/22] target/avr: Add machine none test Michael Rolnik
2019-12-18 21:03 ` [PATCH v39 19/22] target/avr: Update build system Michael Rolnik
2019-12-18 21:03 ` [PATCH v39 20/22] target/avr: Add boot serial test Michael Rolnik
2019-12-18 21:03 ` [PATCH v39 21/22] target/avr: Add Avocado test Michael Rolnik
2019-12-18 21:03 ` [PATCH v39 22/22] target/avr: Update MAINTAINERS file Michael Rolnik
2019-12-23 8:56 ` Aleksandar Markovic
2019-12-23 9:13 ` [PATCH v39 00/22] QEMU AVR 8 bit cores Aleksandar Markovic
2019-12-28 18:01 ` Michael Rolnik
2019-12-28 19:38 ` Aleksandar Markovic
2019-12-28 20:00 ` Michael Rolnik
2019-12-29 14:19 ` Aleksandar Markovic
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