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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:28 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [RFC PATCH 00/13] hw/timer/allwinner: Make it reusable Date: Thu, 19 Dec 2019 19:51:14 +0100 Message-Id: <20191219185127.24388-1-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::332 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi, Niek added the H3 SoC in [1] and noticed in [2] the timer controller is very similar (less timers, watchdog register placed at different address). On 12/18/19 9:14 PM, Niek Linnenbank wrote: > Actually, I copied the timer support code from the existing cubieboard.c > that has > the Allwinner A10, so potentially the same problem is there. > > While looking more closer at this part, I now also discovered that the > timer module from the Allwinner H3 is > mostly a stripped down version of the timer module in the Allwinner A10: > > Allwinner A10, 10.2 Timer Register List, page 85: > https://linux-sunxi.org/images/1/1e/Allwinner_A10_User_manual_V1.5.pdf > > The A10 version has six timers, where the H3 has only two. That should > be fine I would say, the guest would simply > use those available on H3 and ignore the rest. There is however one > conflicting difference: the WDOG0 registers in the Allwinner H3 start > at a different offset and are also different. The current A10 timer does > not currently implement the watchdog part. [...] > So in my opinion its a bit of a trade off here: we can keep it like this > and re-use the A10 timer for now, and perhaps > attempt to generalize that module for proper use in both SoCs. Or we can > introduce a new H3 specific timer module. > What do you think? As an answer to his question, this series is to help him to reuse the A10 timer controller instead of adding a new model to the codebase. [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg665532.html [2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg666304.html Philippe Mathieu-Daudé (13): hw/timer/allwinner: Use the AW_A10_PIT_TIMER_NR definition hw/timer/allwinner: Add AW_PIT_TIMER_MAX definition hw/timer/allwinner: Remove unused definitions hw/timer/allwinner: Move definitions from header to source hw/timer/allwinner: Rename the ptimer field hw/timer/allwinner: Rename 'timer_context' as 'timer' hw/timer/allwinner: Move timer specific fields into AwA10TimerContext hw/timer/allwinner: Add a timer_count field hw/timer/allwinner: Rename AwA10TimerContext as AllwinnerTmrState hw/timer/allwinner: Rename AwA10PITState as AllwinnerTmrCtrlState hw/timer/allwinner: Introduce TYPE_AW_COMMON_PIT abstract device hw/timer/allwinner: Rename AW_A10_PIT() as AW_TIMER_CTRL() hw/timer/allwinner: Rename functions not specific to the A10 SoC include/hw/arm/allwinner-a10.h | 2 +- include/hw/timer/allwinner-a10-pit.h | 54 ++---- hw/timer/allwinner-a10-pit.c | 271 +++++++++++++++++---------- 3 files changed, 192 insertions(+), 135 deletions(-) -- 2.21.0