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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:43 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [RFC PATCH 12/13] hw/timer/allwinner: Rename AW_A10_PIT() as AW_TIMER_CTRL() Date: Thu, 19 Dec 2019 19:51:26 +0100 Message-Id: <20191219185127.24388-13-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This macro is now used by different Allwinner timer controllers, rename it. Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/allwinner-a10-pit.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index ad409b96a1..7413f046cc 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -51,8 +51,8 @@ #define AW_A10_PIT_DEFAULT_CLOCK 0x4 -#define AW_A10_PIT(obj) \ - OBJECT_CHECK(AllwinnerTmrCtrlState, (obj), TYPE_AW_A10_PIT) +#define AW_TIMER_CTRL(obj) \ + OBJECT_CHECK(AllwinnerTmrCtrlState, (obj), TYPE_AW_COMMON_PIT) typedef struct AllwinnerTmrCtrlClass { /*< private >*/ @@ -80,7 +80,7 @@ static void a10_pit_update_irq(AllwinnerTmrCtrlState *s) static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) { - AllwinnerTmrCtrlState *s = AW_A10_PIT(opaque); + AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(opaque); uint8_t index; switch (offset) { @@ -144,7 +144,7 @@ static void a10_pit_set_freq(AllwinnerTmrCtrlState *s, int index) static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - AllwinnerTmrCtrlState *s = AW_A10_PIT(opaque); + AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(opaque); uint8_t index; switch (offset) { @@ -278,7 +278,7 @@ static const VMStateDescription vmstate_a10_pit = { static void a10_pit_reset(DeviceState *dev) { - AllwinnerTmrCtrlState *s = AW_A10_PIT(dev); + AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(dev); uint8_t i; s->irq_enable = 0; @@ -319,7 +319,7 @@ static void a10_pit_timer_cb(void *opaque) static void aw_pit_instance_init(Object *obj) { - AllwinnerTmrCtrlState *s = AW_A10_PIT(obj); + AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(obj); AllwinnerTmrCtrlClass *c = AW_TIMER_GET_CLASS(s); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); uint8_t i; @@ -330,7 +330,7 @@ static void aw_pit_instance_init(Object *obj) sysbus_init_irq(sbd, &s->timer[i].irq); } memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, - TYPE_AW_A10_PIT, c->region_size); + TYPE_AW_COMMON_PIT, c->region_size); sysbus_init_mmio(sbd, &s->iomem); for (i = 0; i < s->timer_count; i++) { -- 2.21.0