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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:44 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [RFC PATCH 13/13] hw/timer/allwinner: Rename functions not specific to the A10 SoC Date: Thu, 19 Dec 2019 19:51:27 +0100 Message-Id: <20191219185127.24388-14-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" These functions are used by different Allwinner timer controllers, rename them. Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/allwinner-a10-pit.c | 52 ++++++++++++++++++------------------ 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 7413f046cc..dff534cfef 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -68,7 +68,7 @@ typedef struct AllwinnerTmrCtrlClass { #define AW_TIMER_GET_CLASS(obj) \ OBJECT_GET_CLASS(AllwinnerTmrCtrlClass, (obj), TYPE_AW_COMMON_PIT) -static void a10_pit_update_irq(AllwinnerTmrCtrlState *s) +static void allwinner_timer_update_irq(AllwinnerTmrCtrlState *s) { int i; @@ -78,7 +78,7 @@ static void a10_pit_update_irq(AllwinnerTmrCtrlState *s) } } -static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) +static uint64_t allwinner_timer_read(void *opaque, hwaddr offset, unsigned size) { AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(opaque); uint8_t index; @@ -125,7 +125,7 @@ static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) } /* Must be called inside a ptimer transaction block for s->timer[idx].ptimer */ -static void a10_pit_set_freq(AllwinnerTmrCtrlState *s, int index) +static void allwinner_ptimer_set_freq(AllwinnerTmrCtrlState *s, int index) { uint32_t prescaler, source, source_freq; @@ -141,8 +141,8 @@ static void a10_pit_set_freq(AllwinnerTmrCtrlState *s, int index) } } -static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, - unsigned size) +static void allwinner_timer_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) { AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(opaque); uint8_t index; @@ -150,11 +150,11 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, switch (offset) { case AW_A10_PIT_TIMER_IRQ_EN: s->irq_enable = value; - a10_pit_update_irq(s); + allwinner_timer_update_irq(s); break; case AW_A10_PIT_TIMER_IRQ_ST: s->irq_status &= ~value; - a10_pit_update_irq(s); + allwinner_timer_update_irq(s); break; case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END: index = offset & 0xf0; @@ -164,7 +164,7 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, case AW_A10_PIT_TIMER_CONTROL: s->timer[index].control = value; ptimer_transaction_begin(s->timer[index].ptimer); - a10_pit_set_freq(s, index); + allwinner_ptimer_set_freq(s, index); if (s->timer[index].control & AW_A10_PIT_TIMER_RELOAD) { ptimer_set_count(s->timer[index].ptimer, s->timer[index].interval); @@ -229,13 +229,13 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, } } -static const MemoryRegionOps a10_pit_ops = { - .read = a10_pit_read, - .write = a10_pit_write, +static const MemoryRegionOps allwinner_timer_ops = { + .read = allwinner_timer_read, + .write = allwinner_timer_write, .endianness = DEVICE_NATIVE_ENDIAN, }; -static Property a10_pit_properties[] = { +static Property allwinner_timer_properties[] = { DEFINE_PROP_UINT32("clk0-freq", AllwinnerTmrCtrlState, clk_freq[0], 0), DEFINE_PROP_UINT32("clk1-freq", AllwinnerTmrCtrlState, clk_freq[1], 0), DEFINE_PROP_UINT32("clk2-freq", AllwinnerTmrCtrlState, clk_freq[2], 0), @@ -276,14 +276,14 @@ static const VMStateDescription vmstate_a10_pit = { } }; -static void a10_pit_reset(DeviceState *dev) +static void allwinner_timer_reset(DeviceState *dev) { AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(dev); uint8_t i; s->irq_enable = 0; s->irq_status = 0; - a10_pit_update_irq(s); + allwinner_timer_update_irq(s); for (i = 0; i < s->timer_count; i++) { s->timer[i].control = AW_A10_PIT_DEFAULT_CLOCK; @@ -291,7 +291,7 @@ static void a10_pit_reset(DeviceState *dev) s->timer[i].count = 0; ptimer_transaction_begin(s->timer[i].ptimer); ptimer_stop(s->timer[i].ptimer); - a10_pit_set_freq(s, i); + allwinner_ptimer_set_freq(s, i); ptimer_transaction_commit(s->timer[i].ptimer); } s->watch_dog_mode = 0; @@ -301,7 +301,7 @@ static void a10_pit_reset(DeviceState *dev) s->count_ctl = 0; } -static void a10_pit_timer_cb(void *opaque) +static void allwinner_ptimer_cb(void *opaque) { AllwinnerTmrState *tc = opaque; AllwinnerTmrCtrlState *s = tc->container; @@ -313,11 +313,11 @@ static void a10_pit_timer_cb(void *opaque) ptimer_stop(s->timer[i].ptimer); s->timer[i].control &= ~AW_A10_PIT_TIMER_EN; } - a10_pit_update_irq(s); + allwinner_timer_update_irq(s); } } -static void aw_pit_instance_init(Object *obj) +static void allwinner_timer_instance_init(Object *obj) { AllwinnerTmrCtrlState *s = AW_TIMER_CTRL(obj); AllwinnerTmrCtrlClass *c = AW_TIMER_GET_CLASS(s); @@ -329,8 +329,8 @@ static void aw_pit_instance_init(Object *obj) for (i = 0; i < s->timer_count; i++) { sysbus_init_irq(sbd, &s->timer[i].irq); } - memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, - TYPE_AW_COMMON_PIT, c->region_size); + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_timer_ops, + s, TYPE_AW_COMMON_PIT, c->region_size); sysbus_init_mmio(sbd, &s->iomem); for (i = 0; i < s->timer_count; i++) { @@ -338,7 +338,7 @@ static void aw_pit_instance_init(Object *obj) tc->container = s; tc->index = i; - s->timer[i].ptimer = ptimer_init(a10_pit_timer_cb, tc, + s->timer[i].ptimer = ptimer_init(allwinner_ptimer_cb, tc, PTIMER_POLICY_DEFAULT); } } @@ -347,8 +347,8 @@ static void aw_timer_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - dc->reset = a10_pit_reset; - dc->props = a10_pit_properties; + dc->reset = allwinner_timer_reset; + dc->props = allwinner_timer_properties; dc->desc = "Allwinner Timer Controller"; dc->vmsd = &vmstate_a10_pit; } @@ -356,7 +356,7 @@ static void aw_timer_class_init(ObjectClass *klass, void *data) static const TypeInfo allwinner_pit_info = { .name = TYPE_AW_COMMON_PIT, .parent = TYPE_SYS_BUS_DEVICE, - .instance_init = aw_pit_instance_init, + .instance_init = allwinner_timer_instance_init, .instance_size = sizeof(AllwinnerTmrCtrlState), .class_init = aw_timer_class_init, .class_size = sizeof(AllwinnerTmrCtrlClass), @@ -379,10 +379,10 @@ static const TypeInfo a10_pit_info = { .class_init = a10_pit_class_init, }; -static void a10_register_types(void) +static void allwinner_timer_register_types(void) { type_register_static(&allwinner_pit_info); type_register_static(&a10_pit_info); } -type_init(a10_register_types); +type_init(allwinner_timer_register_types); -- 2.21.0