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[83.42.66.34]) by smtp.gmail.com with ESMTPSA id b67sm7435494wmc.38.2019.12.19.10.51.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Dec 2019 10:51:38 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Niek Linnenbank Subject: [RFC PATCH 08/13] hw/timer/allwinner: Add a timer_count field Date: Thu, 19 Dec 2019 19:51:22 +0100 Message-Id: <20191219185127.24388-9-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191219185127.24388-1-f4bug@amsat.org> References: <20191219185127.24388-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Beniamino Galvani , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" To be able to support controllers with less than 6 timers, we need a field to be able to iterate over the different count. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/timer/allwinner-a10-pit.h | 1 + hw/timer/allwinner-a10-pit.c | 10 ++++++---- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allwinner-a10-pit.h index e0f864a954..8c64c33f01 100644 --- a/include/hw/timer/allwinner-a10-pit.h +++ b/include/hw/timer/allwinner-a10-pit.h @@ -24,6 +24,7 @@ struct AwA10PITState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ + size_t timer_count; AwA10TimerContext timer[AW_PIT_TIMER_MAX]; MemoryRegion iomem; uint32_t clk_freq[4]; diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index ea92fdda32..3f47588703 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -58,7 +58,7 @@ static void a10_pit_update_irq(AwA10PITState *s) { int i; - for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { + for (i = 0; i < s->timer_count; i++) { qemu_set_irq(s->timer[i].irq, !!(s->irq_status & s->irq_enable & (1 << i))); } @@ -271,7 +271,7 @@ static void a10_pit_reset(DeviceState *dev) s->irq_status = 0; a10_pit_update_irq(s); - for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { + for (i = 0; i < s->timer_count; i++) { s->timer[i].control = AW_A10_PIT_DEFAULT_CLOCK; s->timer[i].interval = 0; s->timer[i].count = 0; @@ -309,14 +309,16 @@ static void a10_pit_init(Object *obj) SysBusDevice *sbd = SYS_BUS_DEVICE(obj); uint8_t i; - for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { + s->timer_count = AW_A10_PIT_TIMER_NR; + + for (i = 0; i < s->timer_count; i++) { sysbus_init_irq(sbd, &s->timer[i].irq); } memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, TYPE_AW_A10_PIT, 0x400); sysbus_init_mmio(sbd, &s->iomem); - for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { + for (i = 0; i < s->timer_count; i++) { AwA10TimerContext *tc = &s->timer[i]; tc->container = s; -- 2.21.0