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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 09/12] hw/arm/smmuv3: Use correct bit positions in EVT_SET_ADDR2 macro
Date: Fri, 20 Dec 2019 14:26:41 +0000	[thread overview]
Message-ID: <20191220142644.31076-10-peter.maydell@linaro.org> (raw)
In-Reply-To: <20191220142644.31076-1-peter.maydell@linaro.org>

From: Simon Veith <sveith@amazon.de>

The bit offsets in the EVT_SET_ADDR2 macro do not match those specified
in the ARM SMMUv3 Architecture Specification. In all events that use
this macro, e.g. F_WALK_EABT, the faulting fetch address or IPA actually
occupies the 32-bit words 6 and 7 in the event record contiguously, with
the upper and lower unused bits clear due to alignment or maximum
supported address bits. How many bits are clear depends on the
individual event type.

Update the macro to write to the correct words in the event record so
that guest drivers can obtain accurate address information on events.

ref. ARM IHI 0070C, sections 7.3.12 through 7.3.16.

Signed-off-by: Simon Veith <sveith@amazon.de>
Acked-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1576509312-13083-6-git-send-email-sveith@amazon.de
Cc: Eric Auger <eric.auger@redhat.com>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Acked-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/smmuv3-internal.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index 042b4358084..4112394129e 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -461,8 +461,8 @@ typedef struct SMMUEventInfo {
     } while (0)
 #define EVT_SET_ADDR2(x, addr)                            \
     do {                                                  \
-            (x)->word[7] = deposit32((x)->word[7], 3, 29, addr >> 16);   \
-            (x)->word[7] = deposit32((x)->word[7], 0, 16, addr & 0xffff);\
+            (x)->word[7] = (uint32_t)(addr >> 32);        \
+            (x)->word[6] = (uint32_t)(addr & 0xffffffff); \
     } while (0)
 
 void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event);
-- 
2.20.1



  parent reply	other threads:[~2019-12-20 14:33 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-20 14:26 [PULL 00/12] target-arm queue Peter Maydell
2019-12-20 14:26 ` [PULL 01/12] target/arm: Remove redundant scaling of nexttick Peter Maydell
2019-12-20 14:26 ` [PULL 02/12] target/arm: Abstract the generic timer frequency Peter Maydell
2019-12-20 14:26 ` [PULL 03/12] target/arm: Prepare generic timer for per-platform CNTFRQ Peter Maydell
2019-12-20 14:26 ` [PULL 04/12] ast2600: Configure CNTFRQ at 1125MHz Peter Maydell
2019-12-20 14:26 ` [PULL 05/12] hw/arm/smmuv3: Apply address mask to linear strtab base address Peter Maydell
2019-12-20 14:26 ` [PULL 06/12] hw/arm/smmuv3: Correct SMMU_BASE_ADDR_MASK value Peter Maydell
2019-12-20 14:26 ` [PULL 07/12] hw/arm/smmuv3: Check stream IDs against actual table LOG2SIZE Peter Maydell
2019-12-20 14:26 ` [PULL 08/12] hw/arm/smmuv3: Align stream table base address to table size Peter Maydell
2019-12-20 14:26 ` Peter Maydell [this message]
2019-12-20 14:26 ` [PULL 10/12] hw/arm/smmuv3: Report F_STE_FETCH fault address in correct word position Peter Maydell
2019-12-20 14:26 ` [PULL 11/12] target/arm: Display helpful message when hflags mismatch Peter Maydell
2019-12-20 14:26 ` [PULL 12/12] arm/arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on() Peter Maydell
2020-01-06 10:32 ` [PULL 00/12] target-arm queue Peter Maydell

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