From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7083CC2D0CE for ; Fri, 3 Jan 2020 03:36:13 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 44CE021D56 for ; Fri, 3 Jan 2020 03:36:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 44CE021D56 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:48302 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1inDkx-0007NP-PF for qemu-devel@archiver.kernel.org; Thu, 02 Jan 2020 22:36:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43618) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1inDiz-0004zS-Jt for qemu-devel@nongnu.org; Thu, 02 Jan 2020 22:34:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1inDiy-00035r-D3 for qemu-devel@nongnu.org; Thu, 02 Jan 2020 22:34:09 -0500 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:53544) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1inDiy-0002uB-3L for qemu-devel@nongnu.org; Thu, 02 Jan 2020 22:34:08 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1174554|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.214826-0.02182-0.763354; DS=||; FP=0|0|0|0|0|-1|-1|-1; HT=e01a16367; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=9; SR=0; TI=SMTPD_---.GV9YvOJ_1578022440; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.GV9YvOJ_1578022440) by smtp.aliyun-inc.com(10.147.42.16); Fri, 03 Jan 2020 11:34:01 +0800 From: LIU Zhiwei To: alistair23@gmail.com, richard.henderson@linaro.org, chihmin.chao@sifive.com, palmer@dabbelt.com Subject: [PATCH v3 1/4] RISC-V: add vector extension field in CPURISCVState Date: Fri, 3 Jan 2020 11:33:44 +0800 Message-Id: <20200103033347.20909-2-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200103033347.20909-1-zhiwei_liu@c-sky.com> References: <20200103033347.20909-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno,offset). Thus elements can be directly accessed by offset from the first vector base address. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0adb307f32..af66674461 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -93,9 +93,23 @@ typedef struct CPURISCVState CPURISCVState; #include "pmp.h" +#define RV_VLEN_MAX 4096 + struct CPURISCVState { target_ulong gpr[32]; uint64_t fpr[32]; /* assume both F and D extensions */ + + /* vector coprocessor state. */ + struct { + uint64_t vreg[32 * RV_VLEN_MAX / 64]; + target_ulong vxrm; + target_ulong vxsat; + target_ulong vl; + target_ulong vstart; + target_ulong vtype; + } vext; + + bool foflag; target_ulong pc; target_ulong load_res; target_ulong load_val; -- 2.23.0