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[79.183.34.164]) by smtp.gmail.com with ESMTPSA id t3sm24870210qtc.8.2020.01.06.23.35.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jan 2020 23:35:42 -0800 (PST) Date: Tue, 7 Jan 2020 02:35:37 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Subject: [PULL v2 06/32] intel_iommu: fix bug to read DMAR_RTADDR_REG Message-ID: <20200107073451.298261-7-mst@redhat.com> References: <20200107073451.298261-1-mst@redhat.com> MIME-Version: 1.0 In-Reply-To: <20200107073451.298261-1-mst@redhat.com> X-Mailer: git-send-email 2.24.1.751.gd10ce2899c X-Mutt-Fcc: =sent X-MC-Unique: G3m3jKvvNdaGHMZlVlcbMg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Yi Sun , Eduardo Habkost , Peter Xu , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Yi Sun Should directly read DMAR_RTADDR_REG but not using 's->root'. Because 's->root' is modified in 'vtd_root_table_setup()' so that the first 12 bits are omitted. This causes the guest iommu debugfs cannot show pasid tables. Signed-off-by: Yi Sun Message-Id: <20191205095439.29114-1-yi.y.sun@linux.intel.com> Signed-off-by: Michael S. Tsirkin Reviewed-by: Peter Xu Reviewed-by: Michael S. Tsirkin --- hw/i386/intel_iommu.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 43c94b993b..ee06993675 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2610,16 +2610,15 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr a= ddr, unsigned size) switch (addr) { /* Root Table Address Register, 64-bit */ case DMAR_RTADDR_REG: + val =3D vtd_get_quad_raw(s, DMAR_RTADDR_REG); if (size =3D=3D 4) { - val =3D s->root & ((1ULL << 32) - 1); - } else { - val =3D s->root; + val =3D val & ((1ULL << 32) - 1); } break; =20 case DMAR_RTADDR_REG_HI: assert(size =3D=3D 4); - val =3D s->root >> 32; + val =3D vtd_get_quad_raw(s, DMAR_RTADDR_REG) >> 32; break; =20 /* Invalidation Queue Address Register, 64-bit */ --=20 MST