* [PATCH RESEND v2 0/4] Add extra information to versioned CPU models
@ 2020-01-08 6:14 Tao Xu
2020-01-08 6:14 ` [PATCH RESEND v2 1/4] target/i386: Add Denverton-v2 (no MPX) CPU model Tao Xu
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Tao Xu @ 2020-01-08 6:14 UTC (permalink / raw)
To: pbonzini, rth, ehabkost; +Cc: tao3.xu, qemu-devel
This series of patches will remove MPX from Denverton, remove Remove
monitor from some CPU models. Add additional information for -cpu help
to indicate the changes in this version of CPU model.
The output is as follows:
./x86_64-softmmu/qemu-system-x86_64 -cpu help | grep "\["
x86 Broadwell-v2 Intel Core Processor (Broadwell) [no TSX]
x86 Broadwell-v3 Intel Core Processor (Broadwell) [IBRS]
x86 Broadwell-v4 Intel Core Processor (Broadwell) [no TSX, IBRS]
x86 Cascadelake-Server-v2 Intel Xeon Processor (Cascadelake) [ARCH_CAPABILITIES]
x86 Cascadelake-Server-v3 Intel Xeon Processor (Cascadelake) [ARCH_CAPABILITIES, no TSX]
x86 Denverton-v2 Intel Atom Processor (Denverton) [no MPX, no MONITOR]
x86 Dhyana-v2 Hygon Dhyana Processor [no MONITOR]
x86 EPYC-v2 AMD EPYC Processor [IBPB]
x86 EPYC-v3 AMD EPYC Processor [IBPB, no MONITOR]
x86 Haswell-v2 Intel Core Processor (Haswell) [no TSX]
x86 Haswell-v3 Intel Core Processor (Haswell) [IBRS]
x86 Haswell-v4 Intel Core Processor (Haswell) [no TSX, IBRS]
x86 Icelake-Client-v2 Intel Core Processor (Icelake) [no TSX]
x86 Icelake-Server-v2 Intel Xeon Processor (Icelake) [no TSX]
x86 IvyBridge-v2 Intel Xeon E3-12xx v2 (Ivy Bridge) [IBRS]
x86 Nehalem-v2 Intel Core i7 9xx (Nehalem Class Core i7) [IBRS]
x86 Opteron_G3-v2 AMD Opteron 23xx (Gen 3 Class Opteron) [no MONITOR]
x86 SandyBridge-v2 Intel Xeon E312xx (Sandy Bridge) [IBRS]
x86 Skylake-Client-v2 Intel Core Processor (Skylake) [IBRS]
x86 Skylake-Client-v3 Intel Core Processor (Skylake) [no TSX, IBRS]
x86 Skylake-Server-v2 Intel Xeon Processor (Skylake) [IBRS]
x86 Skylake-Server-v3 Intel Xeon Processor (Skylake) [no TSX, IBRS]
x86 Snowridge-v2 Intel Atom Processor (SnowRidge) [no MPX]
x86 Snowridge-v3 Intel Atom Processor (SnowRidge) [no MPX, no MONITOR]
x86 Westmere-v2 Westmere E56xx/L56xx/X56xx (Nehalem-C) [IBRS]
Changes in v2:
- Rebase
- correct the note of Cascadelake v3 (Xiaoyao)
Tao Xu (4):
target/i386: Add Denverton-v2 (no MPX) CPU model
target/i386: Remove monitor from some CPU models
target/i386: Add new property note to versioned CPU models
target/i386: Add notes for versioned CPU models
target/i386/cpu.c | 111 +++++++++++++++++++++++++++++++++++-----------
1 file changed, 84 insertions(+), 27 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH RESEND v2 1/4] target/i386: Add Denverton-v2 (no MPX) CPU model
2020-01-08 6:14 [PATCH RESEND v2 0/4] Add extra information to versioned CPU models Tao Xu
@ 2020-01-08 6:14 ` Tao Xu
2020-01-08 6:14 ` [PATCH RESEND v2 2/4] target/i386: Remove monitor from some CPU models Tao Xu
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Tao Xu @ 2020-01-08 6:14 UTC (permalink / raw)
To: pbonzini, rth, ehabkost; +Cc: tao3.xu, qemu-devel
Because MPX is being removed from the linux kernel, remove MPX feature
from Denverton.
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
target/i386/cpu.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 31556b7ec4..6981aa2a34 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3539,6 +3539,18 @@ static X86CPUDefinition builtin_x86_defs[] = {
.features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
.xlevel = 0x80000008,
.model_id = "Intel Atom Processor (Denverton)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ .props = (PropValue[]) {
+ { "monitor", "off" },
+ { "mpx", "off" },
+ { /* end of list */ },
+ },
+ },
+ { /* end of list */ },
+ },
},
{
.name = "Snowridge",
--
2.20.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH RESEND v2 2/4] target/i386: Remove monitor from some CPU models
2020-01-08 6:14 [PATCH RESEND v2 0/4] Add extra information to versioned CPU models Tao Xu
2020-01-08 6:14 ` [PATCH RESEND v2 1/4] target/i386: Add Denverton-v2 (no MPX) CPU model Tao Xu
@ 2020-01-08 6:14 ` Tao Xu
2020-01-08 6:14 ` [PATCH RESEND v2 3/4] target/i386: Add new property note to versioned " Tao Xu
2020-01-08 6:14 ` [PATCH RESEND v2 4/4] target/i386: Add notes for " Tao Xu
3 siblings, 0 replies; 5+ messages in thread
From: Tao Xu @ 2020-01-08 6:14 UTC (permalink / raw)
To: pbonzini, rth, ehabkost; +Cc: tao3.xu, qemu-devel
Add new version of Snowridge, Denverton, Opteron_G3, EPYC, and Dhyana
CPU model to remove MONITOR/MWAIT feature.
After QEMU/KVM use "-overcommit cpu-pm=on" to expose MONITOR/MWAIT
(commit id 6f131f13e68d648a8e4f083c667ab1acd88ce4cd), the MONITOR/MWAIT
feature in these CPU model is unused.
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
target/i386/cpu.c | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6981aa2a34..a6eb1b81fd 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3678,6 +3678,14 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ },
},
},
+ {
+ .version = 3,
+ .props = (PropValue[]) {
+ /* mpx was already removed by -v2 above */
+ { "monitor", "off" },
+ { /* end of list */ },
+ },
+ },
{ /* end of list */ },
},
},
@@ -3789,6 +3797,17 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
.xlevel = 0x80000008,
.model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ .props = (PropValue[]) {
+ { "monitor", "off" },
+ { /* end of list */ },
+ },
+ },
+ { /* end of list */ },
+ },
},
{
.name = "Opteron_G4",
@@ -3913,6 +3932,14 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
+ {
+ .version = 3,
+ .props = (PropValue[]) {
+ /* ibpb was already enabled by -v2 above */
+ { "monitor", "off" },
+ { /* end of list */ },
+ },
+ },
{ /* end of list */ }
}
},
@@ -3965,6 +3992,17 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x8000001E,
.model_id = "Hygon Dhyana Processor",
.cache_info = &epyc_cache_info,
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ .props = (PropValue[]) {
+ { "monitor", "off" },
+ { /* end of list */ },
+ },
+ },
+ { /* end of list */ },
+ },
},
};
--
2.20.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH RESEND v2 3/4] target/i386: Add new property note to versioned CPU models
2020-01-08 6:14 [PATCH RESEND v2 0/4] Add extra information to versioned CPU models Tao Xu
2020-01-08 6:14 ` [PATCH RESEND v2 1/4] target/i386: Add Denverton-v2 (no MPX) CPU model Tao Xu
2020-01-08 6:14 ` [PATCH RESEND v2 2/4] target/i386: Remove monitor from some CPU models Tao Xu
@ 2020-01-08 6:14 ` Tao Xu
2020-01-08 6:14 ` [PATCH RESEND v2 4/4] target/i386: Add notes for " Tao Xu
3 siblings, 0 replies; 5+ messages in thread
From: Tao Xu @ 2020-01-08 6:14 UTC (permalink / raw)
To: pbonzini, rth, ehabkost; +Cc: tao3.xu, qemu-devel
Add additional information for -cpu help to indicate the changes in this
version of CPU model.
Suggested-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
target/i386/cpu.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index a6eb1b81fd..736b4c7326 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1690,6 +1690,7 @@ typedef struct PropValue {
typedef struct X86CPUVersionDefinition {
X86CPUVersion version;
const char *alias;
+ const char *note;
PropValue *props;
} X86CPUVersionDefinition;
@@ -1720,6 +1721,7 @@ struct X86CPUModel {
X86CPUDefinition *cpudef;
/* CPU model version */
X86CPUVersion version;
+ const char *note;
/*
* If true, this is an alias CPU model.
* This matters only for "-cpu help" and query-cpu-definitions
@@ -4846,6 +4848,7 @@ static void x86_cpu_list_entry(gpointer data, gpointer user_data)
g_autofree char *name = x86_cpu_class_get_model_name(cc);
g_autofree char *desc = g_strdup(cc->model_description);
g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc);
+ g_autofree char *model_id = x86_cpu_class_get_model_id(cc);
if (!desc && alias_of) {
if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
@@ -4854,11 +4857,14 @@ static void x86_cpu_list_entry(gpointer data, gpointer user_data)
desc = g_strdup_printf("(alias of %s)", alias_of);
}
}
+ if (!desc && cc->model && cc->model->note) {
+ desc = g_strdup_printf("%s [%s]", model_id, cc->model->note);
+ }
if (!desc) {
- desc = x86_cpu_class_get_model_id(cc);
+ desc = g_strdup_printf("%s", model_id);
}
- qemu_printf("x86 %-20s %-48s\n", name, desc);
+ qemu_printf("x86 %-20s %-58s\n", name, desc);
}
/* list available CPU models and flags */
@@ -5335,6 +5341,7 @@ static void x86_register_cpudef_types(X86CPUDefinition *def)
x86_cpu_versioned_model_name(def, vdef->version);
m->cpudef = def;
m->version = vdef->version;
+ m->note = vdef->note;
x86_register_cpu_model_type(name, m);
if (vdef->alias) {
--
2.20.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH RESEND v2 4/4] target/i386: Add notes for versioned CPU models
2020-01-08 6:14 [PATCH RESEND v2 0/4] Add extra information to versioned CPU models Tao Xu
` (2 preceding siblings ...)
2020-01-08 6:14 ` [PATCH RESEND v2 3/4] target/i386: Add new property note to versioned " Tao Xu
@ 2020-01-08 6:14 ` Tao Xu
3 siblings, 0 replies; 5+ messages in thread
From: Tao Xu @ 2020-01-08 6:14 UTC (permalink / raw)
To: pbonzini, rth, ehabkost; +Cc: tao3.xu, qemu-devel
Add which features are added or removed in this version. Remove the
changed model-id in versioned CPU models.
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
Changes in v2:
- correct the note of Cascadelake v3 (Xiaoyao)
---
target/i386/cpu.c | 50 +++++++++++++++++++++++------------------------
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 736b4c7326..4daa153bfa 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2278,10 +2278,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
{
.version = 2,
.alias = "Nehalem-IBRS",
+ .note = "IBRS",
.props = (PropValue[]) {
{ "spec-ctrl", "on" },
- { "model-id",
- "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
{ /* end of list */ }
}
},
@@ -2359,10 +2358,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
{
.version = 2,
.alias = "Westmere-IBRS",
+ .note = "IBRS",
.props = (PropValue[]) {
{ "spec-ctrl", "on" },
- { "model-id",
- "Westmere E56xx/L56xx/X56xx (IBRS update)" },
{ /* end of list */ }
}
},
@@ -2445,10 +2443,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
{
.version = 2,
.alias = "SandyBridge-IBRS",
+ .note = "IBRS",
.props = (PropValue[]) {
{ "spec-ctrl", "on" },
- { "model-id",
- "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
{ /* end of list */ }
}
},
@@ -2537,10 +2534,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
{
.version = 2,
.alias = "IvyBridge-IBRS",
+ .note = "IBRS",
.props = (PropValue[]) {
{ "spec-ctrl", "on" },
- { "model-id",
- "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
{ /* end of list */ }
}
},
@@ -2634,17 +2630,18 @@ static X86CPUDefinition builtin_x86_defs[] = {
{
.version = 2,
.alias = "Haswell-noTSX",
+ .note = "no TSX",
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
{ "stepping", "1" },
- { "model-id", "Intel Core Processor (Haswell, no TSX)", },
{ /* end of list */ }
},
},
{
.version = 3,
.alias = "Haswell-IBRS",
+ .note = "IBRS",
.props = (PropValue[]) {
/* Restore TSX features removed by -v2 above */
{ "hle", "on" },
@@ -2655,21 +2652,18 @@ static X86CPUDefinition builtin_x86_defs[] = {
*/
{ "stepping", "4" },
{ "spec-ctrl", "on" },
- { "model-id",
- "Intel Core Processor (Haswell, IBRS)" },
{ /* end of list */ }
}
},
{
.version = 4,
.alias = "Haswell-noTSX-IBRS",
+ .note = "no TSX, IBRS",
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
/* spec-ctrl was already enabled by -v3 above */
{ "stepping", "1" },
- { "model-id",
- "Intel Core Processor (Haswell, no TSX, IBRS)" },
{ /* end of list */ }
}
},
@@ -2765,35 +2759,33 @@ static X86CPUDefinition builtin_x86_defs[] = {
{
.version = 2,
.alias = "Broadwell-noTSX",
+ .note = "no TSX",
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
- { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
{ /* end of list */ }
},
},
{
.version = 3,
.alias = "Broadwell-IBRS",
+ .note = "IBRS",
.props = (PropValue[]) {
/* Restore TSX features removed by -v2 above */
{ "hle", "on" },
{ "rtm", "on" },
{ "spec-ctrl", "on" },
- { "model-id",
- "Intel Core Processor (Broadwell, IBRS)" },
{ /* end of list */ }
}
},
{
.version = 4,
.alias = "Broadwell-noTSX-IBRS",
+ .note = "no TSX, IBRS",
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
/* spec-ctrl was already enabled by -v3 above */
- { "model-id",
- "Intel Core Processor (Broadwell, no TSX, IBRS)" },
{ /* end of list */ }
}
},
@@ -2893,17 +2885,17 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
+ .note = "IBRS",
.alias = "Skylake-Client-IBRS",
.props = (PropValue[]) {
{ "spec-ctrl", "on" },
- { "model-id",
- "Intel Core Processor (Skylake, IBRS)" },
{ /* end of list */ }
}
},
{
.version = 3,
.alias = "Skylake-Client-noTSX-IBRS",
+ .note = "no TSX, IBRS",
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
@@ -3014,19 +3006,19 @@ static X86CPUDefinition builtin_x86_defs[] = {
{
.version = 2,
.alias = "Skylake-Server-IBRS",
+ .note = "IBRS",
.props = (PropValue[]) {
/* clflushopt was not added to Skylake-Server-IBRS */
/* TODO: add -v3 including clflushopt */
{ "clflushopt", "off" },
{ "spec-ctrl", "on" },
- { "model-id",
- "Intel Xeon Processor (Skylake, IBRS)" },
{ /* end of list */ }
}
},
{
.version = 3,
.alias = "Skylake-Server-noTSX-IBRS",
+ .note = "no TSX, IBRS",
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
@@ -3138,6 +3130,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.versions = (X86CPUVersionDefinition[]) {
{ .version = 1 },
{ .version = 2,
+ .note = "ARCH_CAPABILITIES",
.props = (PropValue[]) {
{ "arch-capabilities", "on" },
{ "rdctl-no", "on" },
@@ -3149,6 +3142,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
},
{ .version = 3,
.alias = "Cascadelake-Server-noTSX",
+ .note = "ARCH_CAPABILITIES, no TSX",
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
@@ -3321,6 +3315,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
+ .note = "no TSX",
.alias = "Icelake-Client-noTSX",
.props = (PropValue[]) {
{ "hle", "off" },
@@ -3438,6 +3433,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
+ .note = "no TSX",
.alias = "Icelake-Server-noTSX",
.props = (PropValue[]) {
{ "hle", "off" },
@@ -3545,6 +3541,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
+ .note = "no MPX, no MONITOR",
.props = (PropValue[]) {
{ "monitor", "off" },
{ "mpx", "off" },
@@ -3674,14 +3671,15 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
+ .note = "no MPX",
.props = (PropValue[]) {
{ "mpx", "off" },
- { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
{ /* end of list */ },
},
},
{
.version = 3,
+ .note = "no MPX, no MONITOR",
.props = (PropValue[]) {
/* mpx was already removed by -v2 above */
{ "monitor", "off" },
@@ -3803,6 +3801,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
+ .note = "no MONITOR",
.props = (PropValue[]) {
{ "monitor", "off" },
{ /* end of list */ },
@@ -3927,15 +3926,15 @@ static X86CPUDefinition builtin_x86_defs[] = {
{
.version = 2,
.alias = "EPYC-IBPB",
+ .note = "IBPB",
.props = (PropValue[]) {
{ "ibpb", "on" },
- { "model-id",
- "AMD EPYC Processor (with IBPB)" },
{ /* end of list */ }
}
},
{
.version = 3,
+ .note = "IBPB, no MONITOR",
.props = (PropValue[]) {
/* ibpb was already enabled by -v2 above */
{ "monitor", "off" },
@@ -3998,6 +3997,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
+ .note = "no MONITOR",
.props = (PropValue[]) {
{ "monitor", "off" },
{ /* end of list */ },
--
2.20.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-01-08 6:19 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2020-01-08 6:14 [PATCH RESEND v2 0/4] Add extra information to versioned CPU models Tao Xu
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2020-01-08 6:14 ` [PATCH RESEND v2 2/4] target/i386: Remove monitor from some CPU models Tao Xu
2020-01-08 6:14 ` [PATCH RESEND v2 3/4] target/i386: Add new property note to versioned " Tao Xu
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