* [PATCH] target/openrisc: Fix FPCSR mask to allow setting DZF
@ 2020-01-10 21:28 Stafford Horne
2020-01-17 0:51 ` Richard Henderson
0 siblings, 1 reply; 2+ messages in thread
From: Stafford Horne @ 2020-01-10 21:28 UTC (permalink / raw)
To: shorne; +Cc: Openrisc, QEMU Development, Richard Henderson
The mask used when setting FPCSR allows setting bits 10 to 1. However,
OpenRISC has flags and config bits in 11 to 1, 11 being Divide by Zero
Flag (DZF). This seems like an off-by-one bug.
This was found when testing the GLIBC test suite which has test cases to
set and clear all bits.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/fpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c
index 59e1413279..6f75ea0505 100644
--- a/target/openrisc/fpu_helper.c
+++ b/target/openrisc/fpu_helper.c
@@ -70,7 +70,7 @@ void cpu_set_fpcsr(CPUOpenRISCState *env, uint32_t val)
float_round_down
};
- env->fpcsr = val & 0x7ff;
+ env->fpcsr = val & 0xfff;
set_float_rounding_mode(rm_to_sf[extract32(val, 1, 2)], &env->fp_status);
}
--
2.21.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] target/openrisc: Fix FPCSR mask to allow setting DZF
2020-01-10 21:28 [PATCH] target/openrisc: Fix FPCSR mask to allow setting DZF Stafford Horne
@ 2020-01-17 0:51 ` Richard Henderson
0 siblings, 0 replies; 2+ messages in thread
From: Richard Henderson @ 2020-01-17 0:51 UTC (permalink / raw)
To: Stafford Horne; +Cc: Openrisc, QEMU Development, Richard Henderson
On 1/10/20 11:28 AM, Stafford Horne wrote:
> The mask used when setting FPCSR allows setting bits 10 to 1. However,
> OpenRISC has flags and config bits in 11 to 1, 11 being Divide by Zero
> Flag (DZF). This seems like an off-by-one bug.
>
> This was found when testing the GLIBC test suite which has test cases to
> set and clear all bits.
>
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
> target/openrisc/fpu_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Thanks, queued.
r~
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2020-01-17 0:51 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-01-10 21:28 [PATCH] target/openrisc: Fix FPCSR mask to allow setting DZF Stafford Horne
2020-01-17 0:51 ` Richard Henderson
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).