[PATCH v2 0/2] target/arm: Fix ISSIs16Bit

[PATCH v2 0/2] target/arm: Fix ISSIs16Bit

[Richard Henderson]

Changes in v2:
  - Include the merge_syn_data_abort fix, as a self-contained patch.


r~


Jeff Kubascik (1):
  target/arm: Return correct IL bit in merge_syn_data_abort

Richard Henderson (1):
  target/arm: Set ISSIs16Bit in make_issinfo

 target/arm/tlb_helper.c | 2 +-
 target/arm/translate.c  | 3 +++
 2 files changed, 4 insertions(+), 1 deletion(-)

-- 
2.20.1

[PATCH v2 1/2] target/arm: Return correct IL bit in merge_syn_data_abort

[Richard Henderson]

From: Jeff Kubascik <jeff.kubascik@dornerworks.com>

The IL bit is set for 32-bit instructions, thus passing false
with the is_16bit parameter to syn_data_abort_with_iss() makes
a syn mask that always has the IL bit set.

Pass is_16bit as true to make the initial syn mask have IL=0,
so that the final IL value comes from or'ing template_syn.

Cc: qemu-stable@nongnu.org
Fixes: aaa1f954d4ca ("target-arm: A64: Create Instruction Syndromes for Data Aborts")
Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
[rth: Extracted this as a self-contained bug fix from a larger patch]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/tlb_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index 5feb312941..e63f8bda29 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -44,7 +44,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
         syn = syn_data_abort_with_iss(same_el,
                                       0, 0, 0, 0, 0,
                                       ea, 0, s1ptw, is_write, fsc,
-                                      false);
+                                      true);
         /* Merge the runtime syndrome with the template syndrome.  */
         syn |= template_syn;
     }
-- 
2.20.1

[PATCH v2 2/2] target/arm: Set ISSIs16Bit in make_issinfo

[Richard Henderson]

During the conversion to decodetree, the setting of
ISSIs16Bit got lost.  This causes the guest os to
incorrectly adjust trapping memory operations.

Cc: qemu-stable@nongnu.org
Fixes: 46beb58efbb8a2a32 ("target/arm: Convert T16, load (literal)")
Reported-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 5185e08641..c25921ef95 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8556,6 +8556,9 @@ static ISSInfo make_issinfo(DisasContext *s, int rd, bool p, bool w)
     /* ISS not valid if writeback */
     if (p && !w) {
         ret = rd;
+        if (s->base.pc_next - s->pc_curr == 2) {
+            ret |= ISSIs16Bit;
+        }
     } else {
         ret = ISSInvalid;
     }
-- 
2.20.1

Re: [PATCH v2 0/2] target/arm: Fix ISSIs16Bit

[Peter Maydell]

On Fri, 17 Jan 2020 at 00:46, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Changes in v2:
>   - Include the merge_syn_data_abort fix, as a self-contained patch.
>
>
> r~
>


Applied to target-arm.next, thanks. (I didn't cc stable
since it turns out this has been a bug since forever rather
than a new regression introduced by the decodetree conversion.)

-- PMM