* [PATCH] riscv: Fix defination of TW bits in mstatus CSR
@ 2020-01-20 8:58 Ian Jiang
2020-01-21 5:24 ` Alistair Francis
0 siblings, 1 reply; 2+ messages in thread
From: Ian Jiang @ 2020-01-20 8:58 UTC (permalink / raw)
To: qemu-devel; +Cc: Alistair.Francis, palmer, Ian Jiang, sagark, kbastian
The origin defination of TW bits in mstatus is not correct.
This patch fixes the problem.
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
---
target/riscv/cpu_bits.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index e99834856c..fb2e0b340e 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -349,7 +349,7 @@
#define MSTATUS_MXR 0x00080000
#define MSTATUS_VM 0x1F000000 /* until: priv-1.9.1 */
#define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */
-#define MSTATUS_TW 0x20000000 /* since: priv-1.10 */
+#define MSTATUS_TW 0x00200000 /* since: priv-1.10 */
#define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */
#define MSTATUS_MTL 0x4000000000ULL
#define MSTATUS_MPV 0x8000000000ULL
--
2.17.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] riscv: Fix defination of TW bits in mstatus CSR
2020-01-20 8:58 [PATCH] riscv: Fix defination of TW bits in mstatus CSR Ian Jiang
@ 2020-01-21 5:24 ` Alistair Francis
0 siblings, 0 replies; 2+ messages in thread
From: Alistair Francis @ 2020-01-21 5:24 UTC (permalink / raw)
To: Ian Jiang
Cc: Palmer Dabbelt, Alistair Francis,
qemu-devel@nongnu.org Developers, Sagar Karandikar,
Bastian Koppelmann
On Mon, Jan 20, 2020 at 6:59 PM Ian Jiang <ianjiang.ict@gmail.com> wrote:
>
> The origin defination of TW bits in mstatus is not correct.
> This patch fixes the problem.
>
> Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu_bits.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index e99834856c..fb2e0b340e 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -349,7 +349,7 @@
> #define MSTATUS_MXR 0x00080000
> #define MSTATUS_VM 0x1F000000 /* until: priv-1.9.1 */
> #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */
> -#define MSTATUS_TW 0x20000000 /* since: priv-1.10 */
> +#define MSTATUS_TW 0x00200000 /* since: priv-1.10 */
> #define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */
> #define MSTATUS_MTL 0x4000000000ULL
> #define MSTATUS_MPV 0x8000000000ULL
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2020-01-21 5:25 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-01-20 8:58 [PATCH] riscv: Fix defination of TW bits in mstatus CSR Ian Jiang
2020-01-21 5:24 ` Alistair Francis
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).