[PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1

[Palmer Dabbelt <palmerdabbelt@google.com>]

The following changes since commit 28b58f19d269633b3d14b6aebf1e92b3cd3ab56e:

  ui/gtk: Get display refresh rate with GDK version 3.22 or later (2020-01-16 14:03:45 +0000)

are available in the Git repository at:

  git@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-sf1

for you to fetch changes up to 82f014671cf057de51c4a577c9e2ad637dcec6f9:

  target/riscv: update mstatus.SD when FS is set dirty (2020-01-16 10:03:15 -0800)

----------------------------------------------------------------
RISC-V Patches for the 5.0 Soft Freeze, Part 1

This patch set contains a handful of collected fixes that I'd like to target
for the 5.0 soft freeze (I know that's a long way away, I just don't know what
else to call these):

* A fix for a memory leak initializing the sifive_u board.
* Fixes to privilege mode emulation related to interrupts and fstatus.

Notably absent is the H extension implementation.  That's pretty much reviewed,
but not quite ready to go yet and I didn't want to hold back these important
fixes.  This boots 32-bit and 64-bit Linux (buildroot this time, just for fun)
and passes "make check".

----------------------------------------------------------------
Pan Nengyuan (1):
      riscv/sifive_u: fix a memory leak in soc_realize()

ShihPo Hung (3):
      target/riscv: Fix tb->flags FS status
      target/riscv: fsd/fsw doesn't dirty FP state
      target/riscv: update mstatus.SD when FS is set dirty

Yiting Wang (1):
      riscv: Set xPIE to 1 after xRET

 hw/riscv/sifive_u.c                     | 1 +
 target/riscv/cpu.h                      | 5 +----
 target/riscv/csr.c                      | 3 +--
 target/riscv/insn_trans/trans_rvd.inc.c | 1 -
 target/riscv/insn_trans/trans_rvf.inc.c | 1 -
 target/riscv/op_helper.c                | 4 ++--
 target/riscv/translate.c                | 2 +-
 7 files changed, 6 insertions(+), 11 deletions(-)