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From: Palmer Dabbelt <palmerdabbelt@google.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org,       qemu-riscv@nongnu.org,
	ShihPo Hung <shihpo.hung@sifive.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	 Alistair Francis <alistair.francis@wdc.com>,
	Palmer Dabbelt <palmerdabbelt@google.com>
Subject: [PULL 4/5] target/riscv: fsd/fsw doesn't dirty FP state
Date: Tue, 21 Jan 2020 14:57:01 -0800	[thread overview]
Message-ID: <20200121225703.148465-5-palmerdabbelt@google.com> (raw)
In-Reply-To: <20200121225703.148465-1-palmerdabbelt@google.com>

From: ShihPo Hung <shihpo.hung@sifive.com>

Signed-off-by: ShihPo Hung <shihpo.hung@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
 target/riscv/insn_trans/trans_rvd.inc.c | 1 -
 target/riscv/insn_trans/trans_rvf.inc.c | 1 -
 2 files changed, 2 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c
index 393fa0248c..ea1044f13b 100644
--- a/target/riscv/insn_trans/trans_rvd.inc.c
+++ b/target/riscv/insn_trans/trans_rvd.inc.c
@@ -43,7 +43,6 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
 
     tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
 
-    mark_fs_dirty(ctx);
     tcg_temp_free(t0);
     return true;
 }
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c
index 172dbfa919..e23cd639a6 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -52,7 +52,6 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
     tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
 
     tcg_temp_free(t0);
-    mark_fs_dirty(ctx);
     return true;
 }
 
-- 
2.25.0.341.g760bfbb309-goog



  parent reply	other threads:[~2020-01-21 23:45 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-21 22:56 [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1 Palmer Dabbelt
2020-01-21 22:56 ` [PULL 1/5] riscv/sifive_u: fix a memory leak in soc_realize() Palmer Dabbelt
2020-01-21 22:56 ` [PULL 2/5] riscv: Set xPIE to 1 after xRET Palmer Dabbelt
2020-01-21 22:57 ` [PULL 3/5] target/riscv: Fix tb->flags FS status Palmer Dabbelt
2020-01-21 22:57 ` Palmer Dabbelt [this message]
2020-01-21 22:57 ` [PULL 5/5] target/riscv: update mstatus.SD when FS is set dirty Palmer Dabbelt
2020-01-23 14:38 ` [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 1 Peter Maydell
2020-01-23 18:43 ` Palmer Dabbelt
2020-01-24 12:35   ` Peter Maydell
2020-01-27 19:23   ` Palmer Dabbelt
2020-01-24 13:22 ` Peter Maydell

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