From: Ian Jiang <ianjiang.ict@gmail.com>
To: qemu-devel@nongnu.org
Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com,
Ian Jiang <ianjiang.ict@gmail.com>,
sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de
Subject: [PATCH] riscv: Format Rd of FMV.W.X with NoN-boxing
Date: Wed, 22 Jan 2020 15:24:48 +0800 [thread overview]
Message-ID: <20200122072448.18510-1-ianjiang.ict@gmail.com> (raw)
For FMV.W.X that moves the lower 32 bits of an integer register to a
floating-point register, Rd should encoded with NoN-boxing scheme.
Note: This applies to RV64 only.
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
---
target/riscv/insn_trans/trans_rvf.inc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c
index 172dbfa919..62b7a36567 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -368,6 +368,7 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
#if defined(TARGET_RISCV64)
tcg_gen_mov_i64(cpu_fpr[a->rd], t0);
+ tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], 0xffffffff00000000ULL);
#else
tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0);
#endif
--
2.17.1
next reply other threads:[~2020-01-22 7:27 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-22 7:24 Ian Jiang [this message]
2020-01-22 8:53 ` [PATCH] riscv: Format Rd of FMV.W.X with NoN-boxing Richard Henderson
2020-01-22 9:53 ` Ian Jiang
2020-01-22 17:10 ` Richard Henderson
2020-01-23 0:48 ` Ian Jiang
2020-01-23 3:07 ` Richard Henderson
2020-01-23 4:05 ` Ian Jiang
2020-01-23 18:52 ` Richard Henderson
2020-01-27 14:17 ` Ian Jiang
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