From: David Gibson <david@gibson.dropbear.id.au>
To: Oliver O'Halloran <oohall@gmail.com>
Cc: qemu-ppc@nongnu.org, "Cédric Le Goater" <clg@kaod.org>,
"Nicholas Piggin" <npiggin@gmail.com>,
qemu-devel@nongnu.org
Subject: Re: [PATCH 1/2] ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge
Date: Wed, 29 Jan 2020 17:16:35 +1100 [thread overview]
Message-ID: <20200129061635.GA42099@umbus.fritz.box> (raw)
In-Reply-To: <CAOSf1CHvYOMd2cjQDLT44QxyQakkV6a8eBrWX+V6FhQMQh2GWA@mail.gmail.com>
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On Wed, Jan 29, 2020 at 02:54:19PM +1100, Oliver O'Halloran wrote:
> On Wed, Jan 29, 2020 at 2:09 PM David Gibson
> <david@gibson.dropbear.id.au> wrote:
> >
> > On Mon, Jan 27, 2020 at 03:45:05PM +0100, Cédric Le Goater wrote:
> > > From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> > >
>
> *snip*
>
> > > +
> > > +/*
> > > + * The CONFIG_DATA register expects little endian accesses, but as the
> > > + * region is big endian, we have to swap the value.
> > > + */
> > > +static void pnv_phb4_config_write(PnvPHB4 *phb, unsigned off,
> > > + unsigned size, uint64_t val)
> > > +{
> > > + uint32_t cfg_addr, limit;
> > > + PCIDevice *pdev;
> > > +
> > > + pdev = pnv_phb4_find_cfg_dev(phb);
> > > + if (!pdev) {
> > > + return;
> > > + }
> > > + cfg_addr = (phb->regs[PHB_CONFIG_ADDRESS >> 3] >> 32) & 0xffc;
> > > + cfg_addr |= off;
> > > + limit = pci_config_size(pdev);
> > > + if (limit <= cfg_addr) {
> > > + /*
> > > + * conventional pci device can be behind pcie-to-pci bridge.
> > > + * 256 <= addr < 4K has no effects.
> > > + */
> > > + return;
> > > + }
> > > + switch (size) {
> > > + case 1:
> > > + break;
> > > + case 2:
> > > + val = bswap16(val);
> >
> > I'm a little confused by these byteswaps. As I see below the device
> > is set to big endian, so the values passed in here should already be
> > in host-native endian. Why do you need the swap? Are some of the
> > registers in the bank BE and some LE?
>
> All the registers are BE except for CONFIG_DATA, which isn't actually
> a register. It's really a window into the config space of the device
> specified in CONFIG_ADDR so it doesn't do any byte-swapping.
Ah, right, that makes sense.
>
> > > + break;
> > > + case 4:
> > > + val = bswap32(val);
> > > + break;
> > > + default:
> > > + g_assert_not_reached();
> > > + }
> > > + pci_host_config_write_common(pdev, cfg_addr, limit, val, size);
> > > +}
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2020-01-29 6:32 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-27 14:45 [PATCH 0/2] ppc/pnv: Add models for PHB4 and PHB3 PCIe Host bridges Cédric Le Goater
2020-01-27 14:45 ` [PATCH 1/2] ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge Cédric Le Goater
2020-01-29 3:09 ` David Gibson
2020-01-29 3:54 ` Oliver O'Halloran
2020-01-29 6:16 ` David Gibson [this message]
2020-01-27 14:45 ` [PATCH 2/2] ppc/pnv: Add models for POWER8 PHB3 " Cédric Le Goater
2020-01-29 6:31 ` [PATCH 0/2] ppc/pnv: Add models for PHB4 and PHB3 PCIe Host bridges David Gibson
2020-01-29 13:15 ` Cédric Le Goater
2020-01-29 22:14 ` David Gibson
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