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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm3953626pfg.145.2020.01.29.15.56.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2020 15:56:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 00/41] target/arm: Implement ARMv8.1-VHE Date: Wed, 29 Jan 2020 15:55:33 -0800 Message-Id: <20200129235614.29829-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::102e X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Version 5 applies the feedback given vs version 4, back in December. There was quite a bit (thanks) and I believe I've gotten it all. FWIW, the patches without review are: 0028-target-arm-Add-VHE-system-register-redirection-an.patch 0030-target-arm-Flush-tlb-for-ASID-changes-in-EL2-0-tr.patch 0031-target-arm-Flush-tlbs-for-E2-0-translation-regime.patch r~ Alex Bennée (1): target/arm: check TGE and E2H flags for EL0 pauth traps Richard Henderson (40): target/arm: Define isar_feature_aa64_vh target/arm: Enable HCR_E2H for VHE target/arm: Add CONTEXTIDR_EL2 target/arm: Add TTBR1_EL2 target/arm: Update CNTVCT_EL0 for VHE target/arm: Split out vae1_tlbmask target/arm: Split out alle1_tlbmask target/arm: Simplify tlb_force_broadcast alternatives target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 target/arm: Recover 4 bits from TBFLAGs target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits target/arm: Rearrange ARMMMUIdxBit target/arm: Tidy ARMMMUIdx m-profile definitions target/arm: Reorganize ARMMMUIdx target/arm: Add regime_has_2_ranges target/arm: Update arm_mmu_idx for VHE target/arm: Update arm_sctlr for VHE target/arm: Update aa64_zva_access for EL2 target/arm: Update ctr_el0_access for EL2 target/arm: Add the hypervisor virtual counter target/arm: Update timer access for VHE target/arm: Update define_one_arm_cp_reg_with_opaque for VHE target/arm: Add VHE system register redirection and aliasing target/arm: Add VHE timer register redirection and aliasing target/arm: Flush tlb for ASID changes in EL2&0 translation regime target/arm: Flush tlbs for E2&0 translation regime target/arm: Update arm_phys_excp_target_el for TGE target/arm: Update {fp,sve}_exception_el for VHE target/arm: Update get_a64_user_mem_index for VHE target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE target/arm: Enable ARMv8.1-VHE in -cpu max target/arm: Move arm_excp_unmasked to cpu.c target/arm: Pass more cpu state to arm_excp_unmasked target/arm: Use bool for unmasked in arm_excp_unmasked target/arm: Raise only one interrupt in arm_cpu_exec_interrupt target/arm/cpu-param.h | 2 +- target/arm/cpu-qom.h | 1 + target/arm/cpu.h | 423 +++++-------- target/arm/internals.h | 73 ++- target/arm/translate.h | 4 +- target/arm/cpu.c | 162 ++++- target/arm/cpu64.c | 1 + target/arm/debug_helper.c | 50 +- target/arm/helper-a64.c | 2 +- target/arm/helper.c | 1230 +++++++++++++++++++++++++++--------- target/arm/pauth_helper.c | 14 +- target/arm/translate-a64.c | 47 +- target/arm/translate.c | 74 ++- 13 files changed, 1402 insertions(+), 681 deletions(-) -- 2.20.1