From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, alex.bennee@linaro.org,
"Philippe Mathieu-Daudé" <philmd@redhat.com>
Subject: [PATCH v5 06/41] target/arm: Split out vae1_tlbmask
Date: Wed, 29 Jan 2020 15:55:39 -0800 [thread overview]
Message-ID: <20200129235614.29829-7-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200129235614.29829-1-richard.henderson@linaro.org>
No functional change, but unify code sequences.
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 32 +++++++++++++-------------------
1 file changed, 13 insertions(+), 19 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 830f83ae55..20eb8b53c1 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3940,42 +3940,36 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env,
* Page D4-1736 (DDI0487A.b)
*/
+static int vae1_tlbmask(CPUARMState *env)
+{
+ if (arm_is_secure_below_el3(env)) {
+ return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
+ } else {
+ return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
+ }
+}
+
static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
CPUState *cs = env_cpu(env);
- bool sec = arm_is_secure_below_el3(env);
+ int mask = vae1_tlbmask(env);
- if (sec) {
- tlb_flush_by_mmuidx_all_cpus_synced(cs,
- ARMMMUIdxBit_S1SE1 |
- ARMMMUIdxBit_S1SE0);
- } else {
- tlb_flush_by_mmuidx_all_cpus_synced(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0);
- }
+ tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
}
static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
CPUState *cs = env_cpu(env);
+ int mask = vae1_tlbmask(env);
if (tlb_force_broadcast(env)) {
tlbi_aa64_vmalle1is_write(env, NULL, value);
return;
}
- if (arm_is_secure_below_el3(env)) {
- tlb_flush_by_mmuidx(cs,
- ARMMMUIdxBit_S1SE1 |
- ARMMMUIdxBit_S1SE0);
- } else {
- tlb_flush_by_mmuidx(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0);
- }
+ tlb_flush_by_mmuidx(cs, mask);
}
static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
--
2.20.1
next prev parent reply other threads:[~2020-01-30 0:08 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-29 23:55 [PATCH v5 00/41] target/arm: Implement ARMv8.1-VHE Richard Henderson
2020-01-29 23:55 ` [PATCH v5 01/41] target/arm: Define isar_feature_aa64_vh Richard Henderson
2020-01-29 23:55 ` [PATCH v5 02/41] target/arm: Enable HCR_E2H for VHE Richard Henderson
2020-01-31 13:06 ` Peter Maydell
2020-01-31 20:13 ` Richard Henderson
2020-01-29 23:55 ` [PATCH v5 03/41] target/arm: Add CONTEXTIDR_EL2 Richard Henderson
2020-01-29 23:55 ` [PATCH v5 04/41] target/arm: Add TTBR1_EL2 Richard Henderson
2020-01-29 23:55 ` [PATCH v5 05/41] target/arm: Update CNTVCT_EL0 for VHE Richard Henderson
2020-01-29 23:55 ` Richard Henderson [this message]
2020-01-29 23:55 ` [PATCH v5 07/41] target/arm: Split out alle1_tlbmask Richard Henderson
2020-01-29 23:55 ` [PATCH v5 08/41] target/arm: Simplify tlb_force_broadcast alternatives Richard Henderson
2020-01-29 23:55 ` [PATCH v5 09/41] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* Richard Henderson
2020-01-29 23:55 ` [PATCH v5 10/41] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 Richard Henderson
2020-01-29 23:55 ` [PATCH v5 11/41] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* Richard Henderson
2020-01-29 23:55 ` [PATCH v5 12/41] target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01] Richard Henderson
2020-01-29 23:55 ` [PATCH v5 13/41] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 Richard Henderson
2020-01-29 23:55 ` [PATCH v5 14/41] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 Richard Henderson
2020-01-29 23:55 ` [PATCH v5 15/41] target/arm: Recover 4 bits from TBFLAGs Richard Henderson
2020-01-29 23:55 ` [PATCH v5 16/41] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits Richard Henderson
2020-01-29 23:55 ` [PATCH v5 17/41] target/arm: Rearrange ARMMMUIdxBit Richard Henderson
2020-01-29 23:55 ` [PATCH v5 18/41] target/arm: Tidy ARMMMUIdx m-profile definitions Richard Henderson
2020-01-29 23:55 ` [PATCH v5 19/41] target/arm: Reorganize ARMMMUIdx Richard Henderson
2020-01-29 23:55 ` [PATCH v5 20/41] target/arm: Add regime_has_2_ranges Richard Henderson
2020-01-29 23:55 ` [PATCH v5 21/41] target/arm: Update arm_mmu_idx for VHE Richard Henderson
2020-01-29 23:55 ` [PATCH v5 22/41] target/arm: Update arm_sctlr " Richard Henderson
2020-01-29 23:55 ` [PATCH v5 23/41] target/arm: Update aa64_zva_access for EL2 Richard Henderson
2020-01-29 23:55 ` [PATCH v5 24/41] target/arm: Update ctr_el0_access " Richard Henderson
2020-01-29 23:55 ` [PATCH v5 25/41] target/arm: Add the hypervisor virtual counter Richard Henderson
2020-01-29 23:55 ` [PATCH v5 26/41] target/arm: Update timer access for VHE Richard Henderson
2020-01-29 23:56 ` [PATCH v5 27/41] target/arm: Update define_one_arm_cp_reg_with_opaque " Richard Henderson
2020-01-29 23:56 ` [PATCH v5 28/41] target/arm: Add VHE system register redirection and aliasing Richard Henderson
2020-01-31 13:31 ` Peter Maydell
2020-01-29 23:56 ` [PATCH v5 29/41] target/arm: Add VHE timer " Richard Henderson
2020-01-29 23:56 ` [PATCH v5 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime Richard Henderson
2020-01-31 13:11 ` Peter Maydell
2020-01-31 20:19 ` Richard Henderson
2020-01-29 23:56 ` [PATCH v5 31/41] target/arm: Flush tlbs for E2&0 " Richard Henderson
2020-01-31 13:21 ` Peter Maydell
2020-01-29 23:56 ` [PATCH v5 32/41] target/arm: Update arm_phys_excp_target_el for TGE Richard Henderson
2020-01-29 23:56 ` [PATCH v5 33/41] target/arm: Update {fp,sve}_exception_el for VHE Richard Henderson
2020-01-29 23:56 ` [PATCH v5 34/41] target/arm: check TGE and E2H flags for EL0 pauth traps Richard Henderson
2020-01-29 23:56 ` [PATCH v5 35/41] target/arm: Update get_a64_user_mem_index for VHE Richard Henderson
2020-01-29 23:56 ` [PATCH v5 36/41] target/arm: Update arm_cpu_do_interrupt_aarch64 " Richard Henderson
2020-01-29 23:56 ` [PATCH v5 37/41] target/arm: Enable ARMv8.1-VHE in -cpu max Richard Henderson
2020-01-29 23:56 ` [PATCH v5 38/41] target/arm: Move arm_excp_unmasked to cpu.c Richard Henderson
2020-01-29 23:56 ` [PATCH v5 39/41] target/arm: Pass more cpu state to arm_excp_unmasked Richard Henderson
2020-01-29 23:56 ` [PATCH v5 40/41] target/arm: Use bool for unmasked in arm_excp_unmasked Richard Henderson
2020-01-29 23:56 ` [PATCH v5 41/41] target/arm: Raise only one interrupt in arm_cpu_exec_interrupt Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200129235614.29829-7-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=alex.bennee@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=philmd@redhat.com \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).