From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [PATCH v6 31/41] target/arm: Flush tlbs for E2&0 translation regime
Date: Sat, 1 Feb 2020 11:29:06 -0800 [thread overview]
Message-ID: <20200201192916.31796-32-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200201192916.31796-1-richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v5: Flush all EL2 regimes with TLBI ALLE2 (pmm).
---
target/arm/helper.c | 34 +++++++++++++++++++++++++++-------
1 file changed, 27 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index f9be6b052f..0e2278b5aa 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4174,8 +4174,12 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env,
static int vae1_tlbmask(CPUARMState *env)
{
+ /* Since we exclude secure first, we may read HCR_EL2 directly. */
if (arm_is_secure_below_el3(env)) {
return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0;
+ } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE))
+ == (HCR_E2H | HCR_TGE)) {
+ return ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_0;
} else {
return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0;
}
@@ -4219,6 +4223,12 @@ static int alle1_tlbmask(CPUARMState *env)
}
}
+static int alle2_tlbmask(CPUARMState *env)
+{
+ /* TODO: ARMv8.4-SecEL2 */
+ return ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E2;
+}
+
static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -4231,10 +4241,10 @@ static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = env_archcpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
+ int mask = alle2_tlbmask(env);
- tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2);
+ tlb_flush_by_mmuidx(cs, mask);
}
static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4259,8 +4269,9 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
CPUState *cs = env_cpu(env);
+ int mask = alle2_tlbmask(env);
- tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);
+ tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
}
static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4271,6 +4282,15 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3);
}
+static int vae2_tlbmask(CPUARMState *env)
+{
+ if (arm_hcr_el2_eff(env) & HCR_E2H) {
+ return ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E20_2;
+ } else {
+ return ARMMMUIdxBit_E2;
+ }
+}
+
static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -4278,11 +4298,11 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
* Currently handles both VAE2 and VALE2, since we don't support
* flush-last-level-only.
*/
- ARMCPU *cpu = env_archcpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
+ int mask = vae2_tlbmask(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2);
+ tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
}
static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
--
2.20.1
next prev parent reply other threads:[~2020-02-01 19:50 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-01 19:28 [PATCH v6 00/41] target/arm: Implement ARMv8.1-VHE Richard Henderson
2020-02-01 19:28 ` [PATCH v6 01/41] target/arm: Define isar_feature_aa64_vh Richard Henderson
2020-02-01 19:28 ` [PATCH v6 02/41] target/arm: Enable HCR_E2H for VHE Richard Henderson
2020-02-01 19:28 ` [PATCH v6 03/41] target/arm: Add CONTEXTIDR_EL2 Richard Henderson
2020-02-01 19:28 ` [PATCH v6 04/41] target/arm: Add TTBR1_EL2 Richard Henderson
2020-02-01 19:28 ` [PATCH v6 05/41] target/arm: Update CNTVCT_EL0 for VHE Richard Henderson
2020-02-01 19:28 ` [PATCH v6 06/41] target/arm: Split out vae1_tlbmask Richard Henderson
2020-02-01 19:28 ` [PATCH v6 07/41] target/arm: Split out alle1_tlbmask Richard Henderson
2020-02-01 19:28 ` [PATCH v6 08/41] target/arm: Simplify tlb_force_broadcast alternatives Richard Henderson
2020-02-01 19:28 ` [PATCH v6 09/41] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* Richard Henderson
2020-02-01 19:28 ` [PATCH v6 10/41] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 Richard Henderson
2020-02-01 19:28 ` [PATCH v6 11/41] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* Richard Henderson
2020-02-01 19:28 ` [PATCH v6 12/41] target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01] Richard Henderson
2020-02-01 19:28 ` [PATCH v6 13/41] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 Richard Henderson
2020-02-01 19:28 ` [PATCH v6 14/41] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 Richard Henderson
2020-02-01 19:28 ` [PATCH v6 15/41] target/arm: Recover 4 bits from TBFLAGs Richard Henderson
2020-02-01 19:28 ` [PATCH v6 16/41] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits Richard Henderson
2020-02-01 19:28 ` [PATCH v6 17/41] target/arm: Rearrange ARMMMUIdxBit Richard Henderson
2020-02-01 19:28 ` [PATCH v6 18/41] target/arm: Tidy ARMMMUIdx m-profile definitions Richard Henderson
2020-02-01 19:28 ` [PATCH v6 19/41] target/arm: Reorganize ARMMMUIdx Richard Henderson
2020-02-01 19:28 ` [PATCH v6 20/41] target/arm: Add regime_has_2_ranges Richard Henderson
2020-02-01 19:28 ` [PATCH v6 21/41] target/arm: Update arm_mmu_idx for VHE Richard Henderson
2020-02-01 19:28 ` [PATCH v6 22/41] target/arm: Update arm_sctlr " Richard Henderson
2020-02-01 19:28 ` [PATCH v6 23/41] target/arm: Update aa64_zva_access for EL2 Richard Henderson
2020-02-01 19:28 ` [PATCH v6 24/41] target/arm: Update ctr_el0_access " Richard Henderson
2020-02-01 19:29 ` [PATCH v6 25/41] target/arm: Add the hypervisor virtual counter Richard Henderson
2020-02-01 19:29 ` [PATCH v6 26/41] target/arm: Update timer access for VHE Richard Henderson
2020-02-01 19:29 ` [PATCH v6 27/41] target/arm: Update define_one_arm_cp_reg_with_opaque " Richard Henderson
2020-02-01 19:29 ` [PATCH v6 28/41] target/arm: Add VHE system register redirection and aliasing Richard Henderson
2020-02-01 19:29 ` [PATCH v6 29/41] target/arm: Add VHE timer " Richard Henderson
2020-02-01 19:29 ` [PATCH v6 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime Richard Henderson
2020-02-03 11:36 ` Peter Maydell
2020-02-03 11:49 ` Peter Maydell
2020-02-04 13:58 ` Richard Henderson
2020-02-01 19:29 ` Richard Henderson [this message]
2020-02-03 11:30 ` [PATCH v6 31/41] target/arm: Flush tlbs for E2&0 " Peter Maydell
2020-02-01 19:29 ` [PATCH v6 32/41] target/arm: Update arm_phys_excp_target_el for TGE Richard Henderson
2020-02-01 19:29 ` [PATCH v6 33/41] target/arm: Update {fp,sve}_exception_el for VHE Richard Henderson
2020-02-01 19:29 ` [PATCH v6 34/41] target/arm: check TGE and E2H flags for EL0 pauth traps Richard Henderson
2020-02-01 19:29 ` [PATCH v6 35/41] target/arm: Update get_a64_user_mem_index for VHE Richard Henderson
2020-02-01 19:29 ` [PATCH v6 36/41] target/arm: Update arm_cpu_do_interrupt_aarch64 " Richard Henderson
2020-02-01 19:29 ` [PATCH v6 37/41] target/arm: Enable ARMv8.1-VHE in -cpu max Richard Henderson
2020-02-01 19:29 ` [PATCH v6 38/41] target/arm: Move arm_excp_unmasked to cpu.c Richard Henderson
2020-02-01 19:29 ` [PATCH v6 39/41] target/arm: Pass more cpu state to arm_excp_unmasked Richard Henderson
2020-02-01 19:29 ` [PATCH v6 40/41] target/arm: Use bool for unmasked in arm_excp_unmasked Richard Henderson
2020-02-01 19:29 ` [PATCH v6 41/41] target/arm: Raise only one interrupt in arm_cpu_exec_interrupt Richard Henderson
2020-02-03 17:51 ` [PATCH v6 00/41] target/arm: Implement ARMv8.1-VHE Alex Bennée
2020-02-04 14:08 ` Richard Henderson
2020-02-06 10:44 ` Alex Bennée
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