From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, "Alex Bennée" <alex.bennee@linaro.org>
Subject: [PATCH v7 15/41] target/arm: Recover 4 bits from TBFLAGs
Date: Thu, 6 Feb 2020 10:54:22 +0000 [thread overview]
Message-ID: <20200206105448.4726-16-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200206105448.4726-1-richard.henderson@linaro.org>
We had completely run out of TBFLAG bits.
Split A- and M-profile bits into two overlapping buckets.
This results in 4 free bits.
We used to initialize all of the a32 and m32 fields in DisasContext
by assignment, in arm_tr_init_disas_context. Now we only initialize
either the a32 or m32 by assignment, because the bits overlap in
tbflags. So zero the entire structure in gen_intermediate_code.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 68 ++++++++++++++++++++++++++----------------
target/arm/helper.c | 17 +++++------
target/arm/translate.c | 57 +++++++++++++++++++----------------
3 files changed, 82 insertions(+), 60 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a188398b03..fce6a426c8 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3214,6 +3214,16 @@ typedef ARMCPU ArchCPU;
* We put flags which are shared between 32 and 64 bit mode at the top
* of the word, and flags which apply to only one mode at the bottom.
*
+ * 31 21 18 14 9 0
+ * +--------------+-----+-----+----------+--------------+
+ * | | | TBFLAG_A32 | |
+ * | | +-----+----------+ TBFLAG_AM32 |
+ * | TBFLAG_ANY | |TBFLAG_M32| |
+ * | | +-------------------------|
+ * | | | TBFLAG_A64 |
+ * +--------------+-----------+-------------------------+
+ * 31 21 14 0
+ *
* Unless otherwise noted, these bits are cached in env->hflags.
*/
FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1)
@@ -3223,46 +3233,54 @@ FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Not cached. */
/* Target EL if we take a floating-point-disabled exception */
FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2)
FIELD(TBFLAG_ANY, BE_DATA, 23, 1)
-/*
- * For A-profile only, target EL for debug exceptions.
- * Note that this overlaps with the M-profile-only HANDLER and STACKCHECK bits.
- */
+/* For A-profile only, target EL for debug exceptions. */
FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2)
-/* Bit usage when in AArch32 state: */
-FIELD(TBFLAG_A32, THUMB, 0, 1) /* Not cached. */
-FIELD(TBFLAG_A32, VECLEN, 1, 3) /* Not cached. */
-FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) /* Not cached. */
+/*
+ * Bit usage when in AArch32 state, both A- and M-profile.
+ */
+FIELD(TBFLAG_AM32, CONDEXEC, 0, 8) /* Not cached. */
+FIELD(TBFLAG_AM32, THUMB, 8, 1) /* Not cached. */
+
+/*
+ * Bit usage when in AArch32 state, for A-profile only.
+ */
+FIELD(TBFLAG_A32, VECLEN, 9, 3) /* Not cached. */
+FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */
/*
* We store the bottom two bits of the CPAR as TB flags and handle
* checks on the other bits at runtime. This shares the same bits as
* VECSTRIDE, which is OK as no XScale CPU has VFP.
* Not cached, because VECLEN+VECSTRIDE are not cached.
*/
-FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2)
+FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2)
+FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. */
+FIELD(TBFLAG_A32, SCTLR_B, 15, 1)
+FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1)
/*
* Indicates whether cp register reads and writes by guest code should access
* the secure or nonsecure bank of banked registers; note that this is not
* the same thing as the current security state of the processor!
*/
-FIELD(TBFLAG_A32, NS, 6, 1)
-FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */
-FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */
-FIELD(TBFLAG_A32, SCTLR_B, 16, 1)
-FIELD(TBFLAG_A32, HSTR_ACTIVE, 17, 1)
+FIELD(TBFLAG_A32, NS, 17, 1)
-/* For M profile only, set if FPCCR.LSPACT is set */
-FIELD(TBFLAG_A32, LSPACT, 18, 1) /* Not cached. */
-/* For M profile only, set if we must create a new FP context */
-FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) /* Not cached. */
-/* For M profile only, set if FPCCR.S does not match current security state */
-FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) /* Not cached. */
-/* For M profile only, Handler (ie not Thread) mode */
-FIELD(TBFLAG_A32, HANDLER, 21, 1)
-/* For M profile only, whether we should generate stack-limit checks */
-FIELD(TBFLAG_A32, STACKCHECK, 22, 1)
+/*
+ * Bit usage when in AArch32 state, for M-profile only.
+ */
+/* Handler (ie not Thread) mode */
+FIELD(TBFLAG_M32, HANDLER, 9, 1)
+/* Whether we should generate stack-limit checks */
+FIELD(TBFLAG_M32, STACKCHECK, 10, 1)
+/* Set if FPCCR.LSPACT is set */
+FIELD(TBFLAG_M32, LSPACT, 11, 1) /* Not cached. */
+/* Set if we must create a new FP context */
+FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1) /* Not cached. */
+/* Set if FPCCR.S does not match current security state */
+FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1) /* Not cached. */
-/* Bit usage when in AArch64 state */
+/*
+ * Bit usage when in AArch64 state
+ */
FIELD(TBFLAG_A64, TBII, 0, 2)
FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7ee4197456..5609bb18e8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11353,11 +11353,8 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el,
{
uint32_t flags = 0;
- /* v8M always enables the fpu. */
- flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
-
if (arm_v7m_is_handler_mode(env)) {
- flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1);
+ flags = FIELD_DP32(flags, TBFLAG_M32, HANDLER, 1);
}
/*
@@ -11368,7 +11365,7 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el,
if (arm_feature(env, ARM_FEATURE_V8) &&
!((mmu_idx & ARM_MMU_IDX_M_NEGPRI) &&
(env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) {
- flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1);
+ flags = FIELD_DP32(flags, TBFLAG_M32, STACKCHECK, 1);
}
return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
@@ -11561,7 +11558,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S)
!= env->v7m.secure) {
- flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1);
+ flags = FIELD_DP32(flags, TBFLAG_M32, FPCCR_S_WRONG, 1);
}
if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) &&
@@ -11573,12 +11570,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
* active FP context; we must create a new FP context before
* executing any FP insn.
*/
- flags = FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1);
+ flags = FIELD_DP32(flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED, 1);
}
bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK;
if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) {
- flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1);
+ flags = FIELD_DP32(flags, TBFLAG_M32, LSPACT, 1);
}
} else {
/*
@@ -11599,8 +11596,8 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
}
}
- flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb);
- flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits);
+ flags = FIELD_DP32(flags, TBFLAG_AM32, THUMB, env->thumb);
+ flags = FIELD_DP32(flags, TBFLAG_AM32, CONDEXEC, env->condexec_bits);
pstate_for_ss = env->uncached_cpsr;
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 91e2ca5515..c169984374 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10848,38 +10848,48 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
*/
dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) &&
!arm_el_is_aa64(env, 3);
- dc->thumb = FIELD_EX32(tb_flags, TBFLAG_A32, THUMB);
- dc->sctlr_b = FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR_B);
- dc->hstr_active = FIELD_EX32(tb_flags, TBFLAG_A32, HSTR_ACTIVE);
+ dc->thumb = FIELD_EX32(tb_flags, TBFLAG_AM32, THUMB);
dc->be_data = FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE;
- condexec = FIELD_EX32(tb_flags, TBFLAG_A32, CONDEXEC);
+ condexec = FIELD_EX32(tb_flags, TBFLAG_AM32, CONDEXEC);
dc->condexec_mask = (condexec & 0xf) << 1;
dc->condexec_cond = condexec >> 4;
+
core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX);
dc->mmu_idx = core_to_arm_mmu_idx(env, core_mmu_idx);
dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx);
#if !defined(CONFIG_USER_ONLY)
dc->user = (dc->current_el == 0);
#endif
- dc->ns = FIELD_EX32(tb_flags, TBFLAG_A32, NS);
dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL);
- dc->vfp_enabled = FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN);
- dc->vec_len = FIELD_EX32(tb_flags, TBFLAG_A32, VECLEN);
- if (arm_feature(env, ARM_FEATURE_XSCALE)) {
- dc->c15_cpar = FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR);
- dc->vec_stride = 0;
+
+ if (arm_feature(env, ARM_FEATURE_M)) {
+ dc->vfp_enabled = 1;
+ dc->be_data = MO_TE;
+ dc->v7m_handler_mode = FIELD_EX32(tb_flags, TBFLAG_M32, HANDLER);
+ dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) &&
+ regime_is_secure(env, dc->mmu_idx);
+ dc->v8m_stackcheck = FIELD_EX32(tb_flags, TBFLAG_M32, STACKCHECK);
+ dc->v8m_fpccr_s_wrong =
+ FIELD_EX32(tb_flags, TBFLAG_M32, FPCCR_S_WRONG);
+ dc->v7m_new_fp_ctxt_needed =
+ FIELD_EX32(tb_flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED);
+ dc->v7m_lspact = FIELD_EX32(tb_flags, TBFLAG_M32, LSPACT);
} else {
- dc->vec_stride = FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE);
- dc->c15_cpar = 0;
+ dc->be_data =
+ FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE;
+ dc->debug_target_el =
+ FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL);
+ dc->sctlr_b = FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR_B);
+ dc->hstr_active = FIELD_EX32(tb_flags, TBFLAG_A32, HSTR_ACTIVE);
+ dc->ns = FIELD_EX32(tb_flags, TBFLAG_A32, NS);
+ dc->vfp_enabled = FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN);
+ if (arm_feature(env, ARM_FEATURE_XSCALE)) {
+ dc->c15_cpar = FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR);
+ } else {
+ dc->vec_len = FIELD_EX32(tb_flags, TBFLAG_A32, VECLEN);
+ dc->vec_stride = FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE);
+ }
}
- dc->v7m_handler_mode = FIELD_EX32(tb_flags, TBFLAG_A32, HANDLER);
- dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) &&
- regime_is_secure(env, dc->mmu_idx);
- dc->v8m_stackcheck = FIELD_EX32(tb_flags, TBFLAG_A32, STACKCHECK);
- dc->v8m_fpccr_s_wrong = FIELD_EX32(tb_flags, TBFLAG_A32, FPCCR_S_WRONG);
- dc->v7m_new_fp_ctxt_needed =
- FIELD_EX32(tb_flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED);
- dc->v7m_lspact = FIELD_EX32(tb_flags, TBFLAG_A32, LSPACT);
dc->cp_regs = cpu->cp_regs;
dc->features = env->features;
@@ -10901,9 +10911,6 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE);
dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS);
dc->is_ldex = false;
- if (!arm_feature(env, ARM_FEATURE_M)) {
- dc->debug_target_el = FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL);
- }
dc->page_start = dc->base.pc_first & TARGET_PAGE_MASK;
@@ -11340,10 +11347,10 @@ static const TranslatorOps thumb_translator_ops = {
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
{
- DisasContext dc;
+ DisasContext dc = { };
const TranslatorOps *ops = &arm_translator_ops;
- if (FIELD_EX32(tb->flags, TBFLAG_A32, THUMB)) {
+ if (FIELD_EX32(tb->flags, TBFLAG_AM32, THUMB)) {
ops = &thumb_translator_ops;
}
#ifdef TARGET_AARCH64
--
2.20.1
next prev parent reply other threads:[~2020-02-06 11:02 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-06 10:54 [PATCH v7 00/41] target/arm: Implement ARMv8.1-VHE Richard Henderson
2020-02-06 10:54 ` [PATCH v7 01/41] target/arm: Define isar_feature_aa64_vh Richard Henderson
2020-02-06 10:54 ` [PATCH v7 02/41] target/arm: Enable HCR_E2H for VHE Richard Henderson
2020-02-06 10:54 ` [PATCH v7 03/41] target/arm: Add CONTEXTIDR_EL2 Richard Henderson
2020-02-06 10:54 ` [PATCH v7 04/41] target/arm: Add TTBR1_EL2 Richard Henderson
2020-02-06 10:54 ` [PATCH v7 05/41] target/arm: Update CNTVCT_EL0 for VHE Richard Henderson
2020-02-06 10:54 ` [PATCH v7 06/41] target/arm: Split out vae1_tlbmask Richard Henderson
2020-02-06 10:54 ` [PATCH v7 07/41] target/arm: Split out alle1_tlbmask Richard Henderson
2020-02-06 10:54 ` [PATCH v7 08/41] target/arm: Simplify tlb_force_broadcast alternatives Richard Henderson
2020-02-06 10:54 ` [PATCH v7 09/41] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* Richard Henderson
2020-02-06 10:54 ` [PATCH v7 10/41] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 Richard Henderson
2020-02-06 10:54 ` [PATCH v7 11/41] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* Richard Henderson
2020-02-06 10:54 ` [PATCH v7 12/41] target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01] Richard Henderson
2020-02-06 10:54 ` [PATCH v7 13/41] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 Richard Henderson
2020-02-06 10:54 ` [PATCH v7 14/41] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 Richard Henderson
2020-02-06 10:54 ` Richard Henderson [this message]
2020-02-06 10:54 ` [PATCH v7 16/41] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits Richard Henderson
2020-02-06 10:54 ` [PATCH v7 17/41] target/arm: Rearrange ARMMMUIdxBit Richard Henderson
2020-02-06 10:54 ` [PATCH v7 18/41] target/arm: Tidy ARMMMUIdx m-profile definitions Richard Henderson
2020-02-06 10:54 ` [PATCH v7 19/41] target/arm: Reorganize ARMMMUIdx Richard Henderson
2020-02-06 10:54 ` [PATCH v7 20/41] target/arm: Add regime_has_2_ranges Richard Henderson
2020-02-06 10:54 ` [PATCH v7 21/41] target/arm: Update arm_mmu_idx for VHE Richard Henderson
2020-02-06 10:54 ` [PATCH v7 22/41] target/arm: Update arm_sctlr " Richard Henderson
2020-02-06 10:54 ` [PATCH v7 23/41] target/arm: Update aa64_zva_access for EL2 Richard Henderson
2020-02-06 10:54 ` [PATCH v7 24/41] target/arm: Update ctr_el0_access " Richard Henderson
2020-02-06 10:54 ` [PATCH v7 25/41] target/arm: Add the hypervisor virtual counter Richard Henderson
2020-02-06 10:54 ` [PATCH v7 26/41] target/arm: Update timer access for VHE Richard Henderson
2020-02-06 10:54 ` [PATCH v7 27/41] target/arm: Update define_one_arm_cp_reg_with_opaque " Richard Henderson
2020-02-06 10:54 ` [PATCH v7 28/41] target/arm: Add VHE system register redirection and aliasing Richard Henderson
2020-02-06 10:54 ` [PATCH v7 29/41] target/arm: Add VHE timer " Richard Henderson
2020-02-06 10:54 ` [PATCH v7 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime Richard Henderson
2020-02-06 10:54 ` [PATCH v7 31/41] target/arm: Flush tlbs for E2&0 " Richard Henderson
2020-02-06 10:54 ` [PATCH v7 32/41] target/arm: Update arm_phys_excp_target_el for TGE Richard Henderson
2020-02-06 10:54 ` [PATCH v7 33/41] target/arm: Update {fp,sve}_exception_el for VHE Richard Henderson
2020-02-06 10:54 ` [PATCH v7 34/41] target/arm: check TGE and E2H flags for EL0 pauth traps Richard Henderson
2020-02-06 10:54 ` [PATCH v7 35/41] target/arm: Update get_a64_user_mem_index for VHE Richard Henderson
2020-02-06 10:54 ` [PATCH v7 36/41] target/arm: Update arm_cpu_do_interrupt_aarch64 " Richard Henderson
2020-02-06 10:54 ` [PATCH v7 37/41] target/arm: Enable ARMv8.1-VHE in -cpu max Richard Henderson
2020-02-06 10:54 ` [PATCH v7 38/41] target/arm: Move arm_excp_unmasked to cpu.c Richard Henderson
2020-02-06 10:54 ` [PATCH v7 39/41] target/arm: Pass more cpu state to arm_excp_unmasked Richard Henderson
2020-02-06 10:54 ` [PATCH v7 40/41] target/arm: Use bool for unmasked in arm_excp_unmasked Richard Henderson
2020-02-06 10:54 ` [PATCH v7 41/41] target/arm: Raise only one interrupt in arm_cpu_exec_interrupt Richard Henderson
2020-02-07 11:52 ` [PATCH v7 00/41] target/arm: Implement ARMv8.1-VHE Peter Maydell
2020-03-31 15:33 ` Jonathan Cameron
2020-03-31 17:29 ` Jonathan Cameron
2020-03-31 18:59 ` Richard Henderson
2020-04-01 10:45 ` Jonathan Cameron
2020-04-01 16:01 ` Jonathan Cameron
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